Full-Throughput AXI4-Stream Register Slice (Skid Buffer)

RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving Full-Throughput AXI4-Stream Register Slice (Skid Buffer), you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a production-grade 1-stage AXI4-Stream register slice with skid buffering supporting 100% throughput and full timing isolation.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module (
  input  wire        aclk,
  input  wire        aresetn,
  input  wire        s_tvalid,
  output reg         s_tready,
  input  wire [31:0] s_tdata,
  input  wire [3:0]  s_tkeep,
  input  wire        s_tlast,
  output reg         m_tvalid,
  input  wire        m_tready,
  output reg  [31:0] m_tdata,
  output reg  [3:0]  m_tkeep,
  output reg         m_tlast
);

  // Implement a 2-entry skid buffer (Primary and Secondary/Skid registers):
  // Breaks timing paths on both forward (VALID/DATA) and backward (READY) directions.
  // Must sustain 1 transfer per clock cycle when m_tready = 1.

Verified Reference Solution

module top_module (
  input  wire        aclk,
  input  wire        aresetn,
  input  wire        s_tvalid,
  output reg         s_tready,
  input  wire [31:0] s_tdata,
  input  wire [3:0]  s_tkeep,
  input  wire        s_tlast,
  output reg         m_tvalid,
  input  wire        m_tready,
  output reg  [31:0] m_tdata,
  output reg  [3:0]  m_tkeep,
  output reg         m_tlast
);

  // Skid register storage
  reg [31:0] skid_data;
  reg [3:0]  skid_keep;
  reg        skid_last;
  reg        skid_valid;

  always @(posedge aclk or negedge aresetn) begin
    if (!aresetn) begin
      s_tready   <= 1'b1;
      m_tvalid   <= 1'b0;
      m_tdata    <= 32'h0;
      m_tkeep    <= 4'h0;
      m_tlast    <= 1'b0;
      skid_valid <= 1'b0;
      skid_data  <= 32'h0;
      skid_keep  <= 4'h0;
      skid_last  <= 1'b0;
    end else begin
      if (m_tvalid && !m_tready) begin
        // Downstream stalled: capture into skid buffer if new valid beat arrives
        if (s_tvalid && s_tready) begin
          skid_data  <= s_tdata;
          skid_keep  <= s_tkeep;
          skid_last  <= s_tlast;
          skid_valid <= 1'b1;
          s_tready   <= 1'b0; // Skid full: assert backpressure upstream
        end
      end else begin
        // Downstream ready: drain skid if present, otherwise pass from upstream
        if (skid_valid) begin
          m_tvalid   <= 1'b1;
          m_tdata    <= skid_data;
          m_tkeep    <= skid_keep;
          m_tlast    <= skid_last;
          skid_valid <= 1'b0;
          s_tready   <= 1'b1;
        end else if (s_tvalid && s_tready) begin
          m_tvalid <= 1'b1;
          m_tdata  <= s_tdata;
          m_tkeep  <= s_tkeep;
          m_tlast  <= s_tlast;
          s_tready <= 1'b1;
        end else begin
          m_tvalid <= 1'b0;
          s_tready <= 1'b1;
        end
      end
    end
  end

endmodule

Related RTL Problems in Level 6

• Manchester Encoder — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.
• Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
• Quadrature Rotary Encoder Decoder — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.

Frequently Asked Questions