4-Channel Round-Robin AXI-Stream Arbiter with Packet Locking

RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving 4-Channel Round-Robin AXI-Stream Arbiter with Packet Locking, you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design a 4-channel AXI-Stream arbiter featuring packet-boundary locking, starvation-free fair round-robin scheduling, and full backpressure propagation.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module (
  input  wire         aclk,
  input  wire         aresetn,
  input  wire [3:0]   s_tvalid,
  output reg  [3:0]   s_tready,
  input  wire [127:0] s_tdata,
  input  wire [3:0]   s_tlast,
  output reg          m_tvalid,
  input  wire         m_tready,
  output reg  [31:0]  m_tdata,
  output reg          m_tlast
);

  // Implement 4-to-1 Round-Robin Arbiter:
  // 1. Lock arbitration onto winning channel until (m_tvalid && m_tready && m_tlast).
  // 2. Rotate priority to (winner + 1) % 4 only upon packet completion.
  // 3. Forward s_tdata and s_tlast of selected channel to egress.

Verified Reference Solution

module top_module (
  input  wire         aclk,
  input  wire         aresetn,
  input  wire [3:0]   s_tvalid,
  output reg  [3:0]   s_tready,
  input  wire [127:0] s_tdata,
  input  wire [3:0]   s_tlast,
  output reg          m_tvalid,
  input  wire         m_tready,
  output reg  [31:0]  m_tdata,
  output reg          m_tlast
);

  reg [1:0] winner;
  reg [1:0] base_ptr;
  reg       locked;

  wire [31:0] ch_data [0:3];
  assign ch_data[0] = s_tdata[31:0];
  assign ch_data[1] = s_tdata[63:32];
  assign ch_data[2] = s_tdata[95:64];
  assign ch_data[3] = s_tdata[127:96];

  // Combinational round-robin priority picker
  reg [1:0] next_grant;
  reg       any_req;

  always @(*) begin
    any_req    = |s_tvalid;
    next_grant = base_ptr;
    if (s_tvalid[base_ptr]) begin
      next_grant = base_ptr;
    end else if (s_tvalid[(base_ptr + 2'd1) & 2'd3]) begin
      next_grant = (base_ptr + 2'd1) & 2'd3;
    end else if (s_tvalid[(base_ptr + 2'd2) & 2'd3]) begin
      next_grant = (base_ptr + 2'd2) & 2'd3;
    end else if (s_tvalid[(base_ptr + 2'd3) & 2'd3]) begin
      next_grant = (base_ptr + 2'd3) & 2'd3;
    end
  end

  // Mux selection
  always @(*) begin
    if (locked || any_req) begin
      m_tvalid = s_tvalid[winner];
      m_tdata  = ch_data[winner];
      m_tlast  = s_tlast[winner];
    end else begin
      m_tvalid = 1'b0;
      m_tdata  = 32'h0;
      m_tlast  = 1'b0;
    end

    s_tready = 4'b0000;
    if (locked || any_req) begin
      s_tready[winner] = m_tready;
    end
  end

  always @(posedge aclk or negedge aresetn) begin
    if (!aresetn) begin
      winner   <= 2'd0;
      base_ptr <= 2'd0;
      locked   <= 1'b0;
    end else begin
      if (!locked) begin
        if (any_req) begin
          winner <= next_grant;
          locked <= 1'b1;
          // Single-beat packet check
          if (s_tvalid[next_grant] && m_tready && s_tlast[next_grant]) begin
            locked   <= 1'b0;
            base_ptr <= (next_grant + 2'd1) & 2'd3;
          end
        end
      end else begin
        // Locked in transfer
        if (m_tvalid && m_tready && m_tlast) begin
          locked   <= 1'b0;
          base_ptr <= (winner + 2'd1) & 2'd3;
        end
      end
    end
  end

endmodule

Related RTL Problems in Level 6

• Manchester Encoder — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.
• Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
• Quadrature Rotary Encoder Decoder — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.

Frequently Asked Questions