Decoupled AXI4 Write Master Transaction Controller

RTL Problems / Level 6 · Advanced RTL & Protocol Design

What You Will Learn

By solving Decoupled AXI4 Write Master Transaction Controller, you will acquire core industry skills:

• Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
• Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
• Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
• Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Design an AXI4 write master controller handling independent, decoupled address and data channel handshakes with write response tracking.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Timing Constraints & Synthesizable RTL Rules

Architectural Deep Dive & Implementation Walkthrough

Common RTL Designer Pitfalls

Silicon & Hardware Engineering Notes

Starter RTL Code

module top_module (
  input  wire        ACLK,
  input  wire        ARESETn,
  input  wire        start_write,
  input  wire [31:0] wr_addr,
  input  wire [31:0] wr_data,
  output reg         write_complete,
  output reg         write_err,
  output reg         AWVALID,
  input  wire        AWREADY,
  output reg  [31:0] AWADDR,
  output reg         WVALID,
  input  wire        WREADY,
  output reg  [31:0] WDATA,
  output reg         WLAST,
  input  wire        BVALID,
  output reg         BREADY,
  input  wire [1:0]  BRESP

Verified Reference Solution

module top_module (
  input  wire        ACLK,
  input  wire        ARESETn,
  input  wire        start_write,
  input  wire [31:0] wr_addr,
  input  wire [31:0] wr_data,
  output reg         write_complete,
  output reg         write_err,
  output reg         AWVALID,
  input  wire        AWREADY,
  output reg  [31:0] AWADDR,
  output reg         WVALID,
  input  wire        WREADY,
  output reg  [31:0] WDATA,
  output reg         WLAST,
  input  wire        BVALID,
  output reg         BREADY,
  input  wire [1:0]  BRESP
);

  reg aw_done, w_done;

  always @(posedge ACLK or negedge ARESETn) begin
    if (!ARESETn) begin
      write_complete <= 1'b0;
      write_err      <= 1'b0;
      AWVALID        <= 1'b0;
      AWADDR         <= 32'h0;
      WVALID         <= 1'b0;
      WDATA          <= 32'h0;
      WLAST          <= 1'b0;
      BREADY         <= 1'b0;
      aw_done        <= 1'b0;
      w_done         <= 1'b0;
    end else begin
      write_complete <= 1'b0;
      write_err      <= 1'b0;

      if (start_write && !AWVALID && !WVALID && !aw_done && !w_done && !BREADY) begin
        AWVALID <= 1'b1;
        AWADDR  <= wr_addr;
        WVALID  <= 1'b1;
        WDATA   <= wr_data;
        WLAST   <= 1'b1;
        aw_done <= 1'b0;
        w_done  <= 1'b0;
      end

      // Independent AW handshake
      if (AWVALID && AWREADY) begin
        AWVALID <= 1'b0;
        aw_done <= 1'b1;
      end

      // Independent W handshake
      if (WVALID && WREADY) begin
        WVALID <= 1'b0;
        WLAST  <= 1'b0;
        w_done <= 1'b1;
      end

      // When both AW and W have completed, enable B channel
      if ((aw_done || (AWVALID && AWREADY)) && (w_done || (WVALID && WREADY))) begin
        BREADY <= 1'b1;
      end

      // B channel handshake
      if (BREADY && BVALID) begin
        BREADY         <= 1'b0;
        aw_done        <= 1'b0;
        w_done         <= 1'b0;
        write_complete <= 1'b1;
        write_err      <= (BRESP != 2'b00);
      end
    end
  end

endmodule

Related RTL Problems in Level 6

• Manchester Encoder — Combine a data bit with the clock to produce a Manchester-encoded line signal — the self-clocking encoding used in classic Ethernet and RFID.
• Manchester Decoder — Recover the original data bit from a Manchester-encoded line signal — the exact inverse of the Manchester Encoder problem.
• Quadrature Rotary Encoder Decoder — Decode the two-phase A/B signal from a real rotary knob or mouse wheel into a direction and position count — sample B on every rising edge of A.

Frequently Asked Questions