BCD Subtractor

Verilog problems / Combinational Design

What you must build

Subtract two BCD digits and produce a valid BCD result plus a borrow flag — the complement to this catalog's BCD adder.

Engineers use “BCD Subtractor” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [3:0] a,
  input  [3:0] b,
  output [3:0] diff,
  output borrow
);

  // Your code here — borrow = (a<b); diff = borrow ? (a-b+10) : (a-b).

endmodule

Why this shows up in interviews

BCD Subtractor sits under Combinational Design (combinational, arithmetic). Concept: Plain binary subtraction of two BCD digits works fine when the result stays non-negative, but when a < b the binary result would be negative — BCD has no representation for that, so the correction is to add 10 back: diff = a - b + 10 , and raise a borrow flag. Skipping the +10 correction (just computing a - b unconditionally, relying on binary wraparound) produces a value that looks superficially plausible but is not the correct BCD digit — plain two's-complement wraparound and 'add 10' correction are not the same arithmetic.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
• 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
• 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
• 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

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