Binary to One-Cold Decoder

Verilog problems / Combinational Design

What you must build

Decode a 3-bit select into an active-low one-cold output — the polarity every chip-select and enable line on real silicon actually uses.

Engineers use “Binary to One-Cold Decoder” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [2:0] sel,
  output [7:0] out_n
);

  // Your code here — out_n is all 1s except bit [sel], which is 0.

endmodule

Why this shows up in interviews

Binary to One-Cold Decoder sits under Combinational Design (combinational, decoder). Concept: One-cold is the active-low mirror of one-hot: every line idles at 1, and exactly the selected line goes to 0: start from all-1s and clear a single bit, out_n=8'hFF; out_n[sel]=0; . Building an ordinary active-high one-hot instead (start from all-0s, set one bit) is a genuine, common polarity bug — it's the exact bitwise complement of what was asked for, and it would drive real active-low chip-select lines backwards, enabling every device except the one actually selected.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
• 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
• 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
• 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

FAQ