Bit Deinterleaver

Verilog problems / Combinational Design

What you must build

Undo an interleaved byte back into its two original 4-bit streams — the inverse of this catalog's bit interleaver.

Engineers use “Bit Deinterleaver” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [7:0] interleaved,
  output [3:0] a,
  output [3:0] b
);

  // Your code here — a = odd bit positions (7,5,3,1); b = even bit positions (6,4,2,0).

endmodule

Why this shows up in interviews

Bit Deinterleaver sits under Combinational Design (combinational, bit-manipulation). Concept: If a was woven into the odd bit positions and b into the even ones, recovering them is just picking those positions back out: a={interleaved[7],interleaved[5],interleaved[3],interleaved[1]}; b={interleaved[6],interleaved[4],interleaved[2],interleaved[0]} . Swapping which extraction feeds a and which feeds b is the same kind of easy mix-up as building the interleaver backwards — the two recovered nibbles are both real data, they've just traded places.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
• 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
• 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
• 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

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