Verilog problems / Combinational Design
What you must build
Reverse the bit order of an 8-bit word so the LSB becomes the MSB and vice versa — pure rewiring, no arithmetic.
Engineers use “8-Bit Reversal” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.
out = {in[0],in[1],...,in[7]} maps every bit to its mirror position. Confusing this with a byte/nibble swap ({in[3:0],in[7:4]}) reorders groups of bits but leaves each 4-bit half internally unreversed — a very different, and very common, mistake.Port contract
The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.
| Name | Dir | Width | Description |
|---|---|---|---|
| in | input | 8 | Input byte |
| out | output | 8 | in with its bit order fully reversed |
How to approach this kata
This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.
Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.
Starter shape
Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.
module top_module( input [7:0] in, output [7:0] out ); // Your code here — out[i] = in[7-i] for every bit. endmodule
Why this shows up in interviews
8-Bit Reversal sits under Combinational Design (combinational, datapath). Concept: Bit reversal is a straight cross-wiring job: out = {in[0],in[1],...,in[7]} maps every bit to its mirror position. Confusing this with a byte/nibble swap ( {in[3:0],in[7:4]} ) reorders groups of bits but leaves each 4-bit half internally unreversed — a very different, and very common, mistake.
A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.
Related problems
- 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
- 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
- 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
- 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.
FAQ
What does this problem require?
What does the 8-Bit Reversal problem ask for? Reverse the bit order of an 8-bit word so the LSB becomes the MSB and vice versa — pure rewiring, no arithmetic. Implement it as Verilog module top_module with the listed ports.
Combinational or sequential?
Is 8-Bit Reversal combinational or sequential? Tags: combinational, datapath. Follow the clock/reset ports if they appear in the table; if there is no clock, use continuous assignment or combinational always @(*).
How does the auto-grader work?
How is 8-Bit Reversal graded? A hidden SystemVerilog/Verilog testbench in the EcrioniX judge simulates your module in the browser. You pass when every directed vector matches, including the waveform contract shown on this page.