Radix-4 Booth Encoder

Verilog problems / Combinational Design

What you must build

The lookup table at the heart of every fast hardware multiplier: examine 3 overlapping bits of the multiplier and decide whether to add 0, ±1x, or ±2x of the multiplicand this cycle — halving the number of partial products versus naive shift-and-add.

Engineers use “Radix-4 Booth Encoder” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  bHigh,
  input  bCur,
  input  bLow,
  output neg,
  output one_x,
  output two_x
);

  // Your code here — classic radix-4 Booth table on {bHigh,bCur,bLow}:
  // 000->0, 001/010->+1x, 011->+2x, 100->-2x, 101/110->-1x, 111->0.

Why this shows up in interviews

Radix-4 Booth Encoder sits under Combinational Design (combinational, arithmetic, multiplier). Concept: Radix-4 Booth encoding slides a 3-bit window (one bit higher, current, one bit lower) across the multiplier and classifies each window into one of 5 actions: add 0, add/sub 1x, or add/sub 2x the multiplicand — so a multiplier only needs half as many partial-product rows as a plain shift-and-add design. The full 8-entry table is: 000→0, 001/010→+1x, 011→+2x, 100→−2x, 101/110→−1x, 111→0. The easy way to get this wrong is swapping which pattern gets the ×1 weight and which gets the ×2 weight — e.g. encoding 011 (which should be +2x, since it's the boundary where two isolated 1-bits look like a single run ending) as +1x instead. It still produces a plausible-looking partial product, just the wrong magnitude.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
• 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
• 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
• 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

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