Bus Timeout Watchdog

Verilog problems / Sequential Design

What you must build

Flag an error if a bus transaction doesn't get a ready response within a fixed number of cycles — and make sure that error actually clears once a transaction succeeds.

Engineers use “Bus Timeout Watchdog” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  req,
  input  ready,
  output reg timeout_err
);

  // Your code here — count cycles while req is outstanding and ready hasn't arrived.
  // If !req or ready, clear the counter AND timeout_err. At 10 cycles without ready, set timeout_err.

endmodule

Why this shows up in interviews

Bus Timeout Watchdog sits under Sequential Design (sequential, counter, protocol). Concept: The counter resets whenever there's no outstanding request or the slave responds, and the error clears at the same time: if(!req||ready) begin cnt<=0; timeout_err<=0; end . Resetting the counter but forgetting to also clear timeout_err creates a sticky-forever bug: once a transaction times out, even a perfectly healthy later transaction that completes right on time will leave the error flag stuck high, permanently reporting a fault that's no longer true.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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