Byte Sync Detector

Verilog problems / Sequential Design

What you must build

Lock onto a known sync byte in an incoming byte stream and stay locked afterward — the framing step every byte-oriented receiver needs before it can trust word boundaries.

Engineers use “Byte Sync Detector” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  [7:0] byte_in,
  input  byte_valid,
  output reg locked
);

  // Your code here — set locked=1 the first time byte_in==8'hA5 while byte_valid; stay locked afterward.

endmodule

Why this shows up in interviews

Byte Sync Detector sits under Sequential Design (sequential, protocol). Concept: Once a framer spots the sync pattern ( 8'hA5 here), it should latch locked and hold it — later bytes that don't happen to match shouldn't drop the lock, since a real receiver only re-syncs on an explicit resync condition (like reset), not on every non-matching byte. Making the assignment unconditional instead of sticky ( locked <= match instead of if(match) locked<=1 ) causes spurious loss of lock the very next cycle.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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