4-Bit Carry-Select Adder

Verilog problems / Combinational Design

What you must build

Speed up addition by precomputing the upper half twice — once assuming carry-in 0, once assuming carry-in 1 — then muxing in whichever guess turned out right, instead of waiting for the carry to ripple through.

Engineers use “4-Bit Carry-Select Adder” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [3:0] a,
  input  [3:0] b,
  input  cin,
  output [3:0] sum,
  output cout
);

  // Your code here — lower 2 bits add normally with cin; upper 2 bits are computed
  // TWICE (once assuming the lower carry is 0, once assuming it's 1), then muxed
  // by the real lower carry once it's known.

Why this shows up in interviews

4-Bit Carry-Select Adder sits under Combinational Design (combinational, arithmetic, architecture). Concept: A carry-select adder splits the word into blocks; each upper block computes its sum twice in parallel (once for cin=0, once for cin=1) while the lower block's real carry is still being resolved, then a mux instantly picks the correct precomputed result once that carry arrives — trading duplicated hardware for a shorter critical path than a full ripple-carry chain. The whole trick lives in the mux select: sum[3:2] = c1 ? sum1_hi : sum0_hi; . Inverting that select ( ~c1 instead of c1 ) silently swaps in the wrong precomputed half every single time — it still compiles and still looks like a mux-based adder, it just always guesses backwards.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
• 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
• 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
• 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

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