CRC-8 Generator (poly 0x07)

Verilog problems / Protocols & Interfaces

What you must build

Compute an 8-bit CRC over a byte using the classic 0x07 polynomial (CRC-8-CCITT) — the same bit-serial algorithm behind this catalog's CRC-4, scaled up to a full byte.

Engineers use “CRC-8 Generator (poly 0x07)” as a building block in protocols & interfaces. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [7:0] data,
  output [7:0] crc
);

  // Your code here — bit-serial CRC-8 (poly 0x07), processing data MSB-first:
  // fb=crc[7]^bit; crc<<=1; if(fb) crc^=8'h07.

endmodule

Why this shows up in interviews

CRC-8 Generator (poly 0x07) sits under Protocols &amp; Interfaces (combinational, error-correction, protocol). Concept: A bit-serial CRC-8 shifts one bit of the message into an 8-bit register at a time, MSB first: fb=crc[7]^bit; crc=crc<<1; if(fb) crc^=8'h07; , repeated once per input bit. The bit order is the entire algorithm — process the same 8 bits LSB-first instead of MSB-first (an easy mix-up when unrolling the loop) and every single-byte CRC comes out completely different, even though the taps, the polynomial, and the number of iterations are all identical.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• SPI Mode Selector (CPOL/CPHA) — Decode SPI's 4 clocking modes from CPOL and CPHA into the two facts a controller actually needs: what the clock idles at, and which edge samples data.
• APB Slave Register Interface — A minimal AMBA APB slave: 4 registers, zero wait states — and the two-phase setup/access handshake that decides exactly when a write is allowed to land.
• AXI4-Lite Write Channel FSM — Accept an address+data write beat, then hold the response channel until the master acknowledges — the handshake FSM behind every AXI4-Lite peripheral.
• AXI4-Lite Read Channel FSM — The read-side twin of this catalog's AXI4-Lite write FSM: accept an address, then hold the data response until the master accepts it.

FAQ