Intermediate
L3–L4
⏱️ 5–7 weeks
Sequential RTL Design
Understand clocked storage, synchronous vs asynchronous resets, counters, shift registers, and Moore/Mealy FSM design.
Flip-Flop Primitives & Non-Blocking Assignments
Understand D flip-flop edge triggering, setup/hold times, and proper use of non-blocking (<=) operators.
posedge clk triggersNon-blocking assignment rulesRace-condition prevention
Practice RTL Problems (2)
Synchronous vs Asynchronous Reset
Evaluate hardware tradeoffs, glitch vulnerability, and deassertion recovery in reset schemes.
Sync vs async resetReset deassertion recovery timeFPGA dedicated reset pins
Practice RTL Problems (2)
Clock Enables & Clock Gating
Implement synchronous data gating without cutting off clock distribution trees directly.
Data recirculate on enableClock gating vs enable registerDynamic power savings
Practice RTL Problems (2)
Binary Up/Down Counters
Design multi-bit counters with synchronous load, enable, and direction controls.
Mod-2^N countersSynchronous load overrideTerminal count carry-out
Practice RTL Problems (2)
Decade & Modulo Counters
Design non-power-of-two counters with synchronous rollover and glitch-free decode.
Decade Mod-10 countersMod-6 time countersBCD rollover logic
Practice RTL Problems (2)
Shift Registers (SISO, SIPO, PISO)
Construct serial-to-parallel and parallel-to-serial conversion registers for communication interfaces.
SIPO deserializationPISO serializationScan chains
Practice RTL Problems (3)
Edge Detectors & Pulse Generators
Capture rising, falling, and both-edge transitions and emit clean 1-cycle pulses.
Single-stage register delayRising edge (in & ~in_d)1-shot pulse generation
Practice RTL Problems (2)
Ring & Johnson Counters
Design one-hot ring counters and twisted-ring Johnson counters with glitch-free decoding.
One-hot circulating tokenJohnson 2N state countSelf-correcting state recovery
Practice RTL Problems (2)
Moore Finite State Machines
Implement 3-block Moore FSMs where outputs depend solely on current state registers.
State register, next-state logic, output logicGlitch-free outputsSequence detection
Practice RTL Problems (2)
Mealy Finite State Machines & Overlap Detection
Design Mealy FSMs with immediate input-dependent outputs and compare against Moore latency.
Mealy vs Moore tradeoffsOverlapping vs non-overlapping patternsOutput register retiming
Practice RTL Problems (2)
Why Master Sequential RTL Design?
Design robust finite state machines and synchronous sequential controllers free of hold/setup hazards. Engineers who excel in this curriculum consistently outperform in technical interviews at semiconductor leaders such as NVIDIA, Qualcomm, Apple, and Intel because this roadmap focuses on synthesizability, edge-case assertions, and real simulation waveforms rather than purely theoretical textbook logic.
Recommended Learning Methodology
- Step 1 — Understand the Concept: Read each module's core objectives and referenced EcrioniX guide.
- Step 2 — Code the RTL: Open each practice challenge and implement
top_module matching the exact ports and timing contract.
- Step 3 — Inspect Waveforms: Run the remote cloud simulator to generate timing waveforms (VCD). Compare your signal transitions with the golden WaveDrom contract.
- Step 4 — Review Explanations: Even after passing, review the editorial notes and hardware considerations to understand ASIC synthesis tradeoffs.
Frequently Asked Questions
What tools do I need for this roadmap?
None! All simulation testbenches run in the browser using our remote Icarus Verilog runner with automated waveform generation.
Are the reference solutions accessible?
Yes. Reference solutions are protected in an expandable solution drawer. We strongly encourage attempting and simulating your own RTL first.