Direct-Mapped Cache Lookup

Verilog problems / Sequential Design

What you must build

A 4-line direct-mapped cache that auto-allocates on a miss — the tag-compare-and-fill loop every real cache runs, shrunk down to something you can trace by hand.

Engineers use “Direct-Mapped Cache Lookup” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  access,
  input  [3:0] addr,
  output hit
);

  // Your code here — 4-line direct-mapped cache: addr[1:0]=index, addr[3:2]=tag.
  // hit = access && valid[index] && tag_store[index]==tag.
  // On a miss (access && !hit), synchronously allocate: tag_store[index]<=tag; valid[index]<=1.

Why this shows up in interviews

Direct-Mapped Cache Lookup sits under Sequential Design (sequential, memory, cache). Concept: Each address splits into an index (which line it maps to) and a tag (which of the many possible blocks currently occupies that line). A hit requires both the line to hold valid data and its stored tag to match: hit = access && valid[idx] && (tag_store[idx]==tag) . Dropping the valid check is a genuinely dangerous real-world bug, not just a cosmetic one: an uninitialized or just-reset tag array reads back as some fixed value (often all-zero), so any address whose tag happens to equal that value reports a false hit against a line that was never actually filled — silently returning garbage as if it were valid cached data.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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