DMA Descriptor Beat Counter

Verilog problems / Sequential Design

What you must build

Track remaining beats in a DMA transfer as they complete, guarding against the stray late-arriving pulse that real pipelined DMA engines can produce after completion.

Engineers use “DMA Descriptor Beat Counter” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  load,
  input  [7:0] beat_total,
  input  beat_done,
  output reg [7:0] beats_remaining,
  output xfer_complete
);

  // Your code here — load sets beats_remaining=beat_total. beat_done decrements, but only if !=0.
  // xfer_complete = (beats_remaining==0).

Why this shows up in interviews

DMA Descriptor Beat Counter sits under Sequential Design (sequential, counter, dma). Concept: The remaining-beats counter must never decrement past 0 — if(beat_done && beats_remaining!=0) beats_remaining<=beats_remaining-1 — because a real DMA engine's completion pulses can arrive slightly out of sync with the counter due to pipeline latency, and a stray extra pulse after the transfer is already done is a normal, expected occurrence, not an error. Skip the guard and that harmless extra pulse underflows the counter to 255, which then flips xfer_complete back to 0 — telling the rest of the system a finished transfer is somehow still in progress.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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