Verilog problems / Fun & Games
What you must build
The classic programming-interview puzzle, recast as combinational hardware: classify a number as Fizz, Buzz, FizzBuzz, or itself.
Engineers use “FizzBuzz Encoder” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.
n%3==0 is true, so the circuit reports plain "Fizz" and the FizzBuzz branch below it becomes permanently unreachable dead code for every multiple of 15.Port contract
The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.
| Name | Dir | Width | Description |
|---|---|---|---|
| n | input | 8 | Number to classify |
| result | output | 2 | 0=number, 1=Fizz (div by 3), 2=Buzz (div by 5), 3=FizzBuzz (div by 15) |
How to approach this kata
This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.
Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.
Starter shape
Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.
module top_module( input [7:0] n, output [1:0] result ); // Your code here — check divisible-by-15 FIRST, then by-3, then by-5, else 0. endmodule
Why this shows up in interviews
FizzBuzz Encoder sits under Fun & Games (combinational, arithmetic). Concept: The one rule that trips people up in software trips up hardware too: the divisible-by-15 ("FizzBuzz") case must be checked before the individual divisible-by-3 and divisible-by-5 cases, because every multiple of 15 is also a multiple of 3 (and of 5) — check order matters. Checking divisible-by-3 first is the textbook FizzBuzz bug: for n=15, n%3==0 is true, so the circuit reports plain "Fizz" and the FizzBuzz branch below it becomes permanently unreachable dead code for every multiple of 15.
A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.
Related problems
- Simon Says Sequence Checker — Check a player's button presses against a fixed 4-step target sequence, one press at a time — freeze on the first mistake, celebrate after the last correct press.
- Parking Meter Timer — A coin-fed countdown timer that flags a violation the instant time runs out and no more coins arrive — a real-world countdown-with-guard pattern.
- Top-3 Leaderboard Tracker — Maintain the 3 highest scores seen so far in sorted order as new scores stream in — an insertion-sort shift register in miniature.
- Leap Year Checker — Determine whether a given year is a leap year — the classic "divisible by 4, except by 100, except-except by 400" rule as combinational logic.
FAQ
What does this problem require?
What does the FizzBuzz Encoder problem ask for? The classic programming-interview puzzle, recast as combinational hardware: classify a number as Fizz, Buzz, FizzBuzz, or itself. Implement it as Verilog module top_module with the listed ports.
Combinational or sequential?
Is FizzBuzz Encoder combinational or sequential? Tags: combinational, arithmetic. Follow the clock/reset ports if they appear in the table; if there is no clock, use continuous assignment or combinational always @(*).
How does the auto-grader work?
How is FizzBuzz Encoder graded? A hidden SystemVerilog/Verilog testbench in the EcrioniX judge simulates your module in the browser. You pass when every directed vector matches, including the waveform contract shown on this page.