I2C Start/Stop Condition Detector

Verilog problems / Sequential Design

What you must build

Detect the two conditions that frame every I2C transaction: SDA falling while SCL is high (START) and SDA rising while SCL is high (STOP) — the one rule that makes I2C's bus protocol work at all.

Engineers use “I2C Start/Stop Condition Detector” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  sda,
  input  scl,
  output reg start_detected,
  output reg stop_detected
);

  // Your code here — register sda/scl; start=SDA falls while SCL held high; stop=SDA rises while SCL held high.

endmodule

Why this shows up in interviews

I2C Start/Stop Condition Detector sits under Sequential Design (sequential, protocol, i2c). Concept: I2C is unique among serial buses: data (SDA) is only allowed to change while the clock (SCL) is low — every SDA transition while SCL is high is a special framing signal, not a data bit. Falling SDA while SCL stays high marks START; rising SDA while SCL stays high marks STOP. Detecting this needs registered previous samples of both signals: start <= scl && scl_prev && sda_prev && !sda . Swapping which edge means start and which means stop is a genuinely easy mix-up (both rules look almost identical at a glance) — and it inverts the meaning of every transaction boundary in the bus trace.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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