Interrupt Mask Register

Verilog problems / Combinational Design

What you must build

Gate a bank of interrupt sources through a per-bit mask so that masked-off interrupts never reach the CPU — the register-level building block behind every real interrupt controller.

Engineers use “Interrupt Mask Register” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [7:0] irq,
  input  [7:0] mask,
  output [7:0] pending,
  output irq_out
);

  // Your code here — pending = irq & mask; irq_out = |pending (NOT |irq).

endmodule

Why this shows up in interviews

Interrupt Mask Register sits under Combinational Design (combinational, interrupt). Concept: The masked interrupt bits ( pending = irq & mask ) are only half the job — the final line to the CPU must come from pending , not from the raw irq bits: irq_out = |pending . A very real bug when a mask register gets bolted onto an existing controller is computing pending correctly but leaving the old irq_out = |irq driver untouched — the masked-pending bits look right in isolation, but the interrupt line to the CPU is still driven straight from the unmasked sources, so masking a source does nothing at all to whether it actually interrupts.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
• 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
• 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
• 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

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