Leap Year Checker

Verilog problems / Fun & Games

What you must build

Determine whether a given year is a leap year — the classic "divisible by 4, except by 100, except-except by 400" rule as combinational logic.

Engineers use “Leap Year Checker” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is an introductory kata. Prefer a clear continuous assignment or a small combinational always block. Name the module top_module and keep the port list identical to the table — the hidden testbench instantiates that name.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [11:0] year,
  output is_leap
);

  // Your code here — is_leap = divisible by 4 AND (not divisible by 100 OR divisible by 400).

endmodule

Why this shows up in interviews

Leap Year Checker sits under Fun & Games (combinational, arithmetic). Concept: The full leap-year rule has three layers: divisible by 4 is required; being also divisible by 100 normally disqualifies it — unless it's divisible by 400 too, in which case it's a leap year after all: (year%4==0) && ((year%100!=0) || (year%400==0)) . The simplified two-layer version most people remember ("divisible by 4 and not by 100") gets every ordinary year right and only fails on the rare century-year exception — real years like 2000 (a leap year, since it's divisible by 400) and 1900 (not a leap year) are exactly the edge cases that expose the missing third layer.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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