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Part of Curriculum: Verilog Fundamentals (Module 3: Basic Logic Gates (AND, OR, XOR))
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Level 1 Easy 10 pts ✓ Solved

2-Input OR Gate

Digital Logic Fundamentals · combinational, gates

Implement a 2-input OR gate. The output is 1 if either input is 1.

Module Specification
Write a synthesizable Verilog module named top_module matching the ports below exactly.
📐 Circuit Schematic Diagram
aboutOR
⚡ Timing & Synthesizability Constraints

Timing Contract: Strict synchronous timing aligned to posedge clk or zero-delay combinational propagation.

RTL Constraints: Synthesizable Verilog-2001. No # delays in synthesizable RTL.

Concept: bitwise OR. Use assign out = a | b;. The output is 0 only when both inputs are 0.
Port Contract
NameDirWidthDescription
ainput1First input operand
binput1Second input operand
outoutput1a OR b
Expected Waveform (Golden Timing Contract)
Verilog-2001 / SV Saved
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Open Simulation Lab
// Click Run Tests (or press Ctrl+Enter) to compile your RTL and simulate against hidden testbenches.
Simulation Timing Diagram (VCD Waveform)
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RTL Problems / Level 1 · Digital Logic Fundamentals

What You Will Learn

By solving 2-Input OR Gate, you will acquire core industry skills:

  • Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
  • Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
  • Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
  • Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Implement a 2-input OR gate. The output is 1 if either input is 1.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Concept: bitwise OR. Use assign out = a | b;. The output is 0 only when both inputs are 0.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

NameDirWidthDescription
ainput1First input operand
binput1Second input operand
outoutput1a OR b

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Strict synchronous timing aligned to posedge clk or zero-delay combinational propagation.

Synthesis Constraints: Synthesizable Verilog-2001. No # delays in synthesizable RTL.

Starter RTL Code

module top_module(
  input  a,
  input  b,
  output out
);

  // Your code here

endmodule

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Frequently Asked Questions

What does 2-Input OR Gate require?

Implement a 2-input OR gate. The output is 1 if either input is 1. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: combinational, gates. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of 2-Input OR Gate to assess real-world synthesizability and race-condition awareness.