Reaction Game Scorer

Verilog problems / Fun & Games

What you must build

Score a simple reflex game: a light comes on, the player presses a button, and the circuit measures how many cycles it took — flagging jumping the gun or dozing off.

Engineers use “Reaction Game Scorer” as a building block in fun & games. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  stimulus,
  input  button,
  output reg [3:0] reaction_time,
  output reg too_slow,
  output reg too_early,
  output reg valid
);

  // Your code here — idle: too_early if button pressed with no stimulus yet, else move to armed on stimulus.

Why this shows up in interviews

Reaction Game Scorer sits under Fun & Games (sequential, fsm, game-logic). Concept: A 3-state FSM (idle → armed → done) times the gap between stimulus and button : pressing before the stimulus is too_early , pressing within the window gives a valid reaction_time, and letting a counter hit a fixed threshold without a press sets too_slow . That timeout check is the easy piece to forget — an implementation that only reacts to button in the armed state and never checks whether the counter has run out will simply wait forever for a press that never comes, silently dropping the entire "too slow" case instead of ever flagging it.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

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