Advanced
L5–L8
⏱️ 5–8 weeks
Memory and FIFO Design
From single-port SRAM inference to parameterized synchronous FIFOs, programmable watermarks, and dual-clock asynchronous FIFOs.
Synchronous RAM Inference & Memory Arrays
Infer block RAMs (BRAM) using synthesizable Verilog array syntax with synchronous write enables.
reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]Write-first vs read-firstAddress registers
Practice RTL Problems (2)
Dual-Port RAM & Register Files
Implement multi-read, single-write register files with write-through forwarding.
Dual-port read accessSimultaneous read/write to same addressForwarding multiplexers
Practice RTL Problems (2)
Synchronous FIFO Fundamentals
Build single-clock circular FIFO buffers managing write pointers, read pointers, and entry counts.
Circular pointerswr_en && !full push logicrd_en && !empty pop logic
Practice RTL Problems (1)
Pointer MSB Wraparound & Full/Empty Detection
Distinguish full from empty capacity using an extra MSB wrap-around bit on pointers.
N+1 bit pointer techniqueMSB inverted with lower bits equal = FULLZero hardware count storage
Practice RTL Problems (1)
FIFO Occupancy & Available Space Tracking
Maintain precise word occupancy counters with simultaneous push and pop handling.
Count up/down logicZero delta on simultaneous push/popCapacity headroom
Practice RTL Problems (1)
Programmable Watermarks (Almost-Full / Almost-Empty)
Generate proactive flow control threshold signals to absorb pipeline latency.
Almost-full watermarkAlmost-empty watermarkThreshold register comparators
Practice RTL Problems (2)
Parameterized Full-Bandwidth Synchronous FIFO
Design a parameterizable synchronous FIFO supporting continuous simultaneous read and write even when full.
Simultaneous push/pop when fullFirst-word fall-through (FWFT)Zero idle bubbles
Practice RTL Problems (1)
Gray Code Pointers & Conversion Mechanics
Convert binary pointers to Gray code and back, ensuring exactly 1-bit transitions across multi-bit words.
Binary to Gray (b ^ (b >> 1))Gray to Binary conversionMetastability reduction
Practice RTL Problems (2)
Asynchronous Pointer Cross-Domain Synchronization
Pass Gray pointers across unrelated write and read clocks using 2-stage flip-flop synchronizers.
2-flop Gray pointer CDCMulti-cycle path constraintsPointer pessimism
Practice RTL Problems (1)
Complete Dual-Clock Asynchronous FIFO
Implement a full dual-clock asynchronous FIFO with safe full/empty flags, zero data loss, and ASIC synthesis pragmas.
Write domain full generationRead domain empty generation(* ASYNC_REG = "TRUE" *)set_max_delay -datapath_only
Practice RTL Problems (1)
Why Master Memory and FIFO Design?
Implement silicon-proven FIFO queues capable of sustained 100% throughput without underflow or overflow. Engineers who excel in this curriculum consistently outperform in technical interviews at semiconductor leaders such as NVIDIA, Qualcomm, Apple, and Intel because this roadmap focuses on synthesizability, edge-case assertions, and real simulation waveforms rather than purely theoretical textbook logic.
Recommended Learning Methodology
- Step 1 — Understand the Concept: Read each module's core objectives and referenced EcrioniX guide.
- Step 2 — Code the RTL: Open each practice challenge and implement
top_module matching the exact ports and timing contract.
- Step 3 — Inspect Waveforms: Run the remote cloud simulator to generate timing waveforms (VCD). Compare your signal transitions with the golden WaveDrom contract.
- Step 4 — Review Explanations: Even after passing, review the editorial notes and hardware considerations to understand ASIC synthesis tradeoffs.
Frequently Asked Questions
What tools do I need for this roadmap?
None! All simulation testbenches run in the browser using our remote Icarus Verilog runner with automated waveform generation.
Are the reference solutions accessible?
Yes. Reference solutions are protected in an expandable solution drawer. We strongly encourage attempting and simulating your own RTL first.