Serial-to-Parallel Receiver with Parity

Verilog problems / Sequential Design

What you must build

Receive an 8-bit word one bit at a time, MSB first, followed by an even-parity check bit — and flag a mismatch instead of silently trusting corrupted data.

Engineers use “Serial-to-Parallel Receiver with Parity” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  bit_in,
  input  frame_start,
  output reg [7:0] data_out,
  output reg parity_error,
  output reg data_valid
);

  // Your code here — shift in 8 data bits MSB-first, then check the 9th bit against even parity (XOR of the 8 data bits).

Why this shows up in interviews

Serial-to-Parallel Receiver with Parity sits under Sequential Design (sequential, protocol). Concept: After a framing pulse, shift in 8 data bits MSB-first ( shreg <= {shreg[6:0], bit_in} ), then treat the 9th bit as an even-parity check: for even parity, the correct check bit always equals the XOR of the 8 data bits, so parity_error = (^shreg) != bit_in . Inverting that comparison ( == instead of != ) flips the entire meaning of the flag — every good frame gets reported as corrupted and every actually-corrupted frame sails through as clean, which is far more dangerous than having no parity check at all.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ