Sign-Magnitude to Two's-Complement Converter

Verilog problems / Combinational Design

What you must build

Convert a 4-bit sign-magnitude number (top bit = sign, bottom 3 bits = magnitude) into standard two's-complement.

Engineers use “Sign-Magnitude to Two's-Complement Converter” as a building block in combinational design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a medium kata: you will need sequential logic or a small FSM. Decide what is registered versus combinational before you type. Reset polarity and clock edge must match the spec; the judge will fail you on the first mismatched cycle.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  [3:0] in,
  output [3:0] out
);

  // Your code here — in[3]=sign, in[2:0]=magnitude; convert to two's-complement.

endmodule

Why this shows up in interviews

Sign-Magnitude to Two's-Complement Converter sits under Combinational Design (combinational, arithmetic). Concept: Sign-magnitude and two's-complement agree on positive numbers but disagree on negatives. Build the zero-extended magnitude, mag = {1'b0, in[2:0]} , then negate it (invert and add 1) only when the sign bit is set: out = in[3] ? (~mag + 1) : in; . Skipping the "+1" gives one's-complement instead — a common off-by-one bug.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• 2-to-1 Multiplexer — Select between two 1-bit inputs using sel. When sel=0 output a; when sel=1 output b.
• 1-Bit Full Adder — Compute sum and carry-out for a + b + cin.
• 4-to-1 Multiplexer — Select one of four 1-bit inputs using a 2-bit sel. sel=00→in0, 01→in1, 10→in2, 11→in3.
• 4-to-2 Priority Encoder — Output the index of the highest-priority (MSB-most) set bit in a 4-bit input, plus a valid flag when any bit is set.

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