UART Frame Assembler

Verilog problems / Sequential Design

What you must build

Detect a UART start bit on a serial line, shift in 8 data bits LSB-first, and flag the completed byte for exactly one cycle.

Engineers use “UART Frame Assembler” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  rx,
  output reg [7:0] rx_data,
  output reg rx_valid
);

  // Your code here — idle until rx falls (start bit), shift in 8 bits LSB-first, pulse rx_valid for 1 cycle when done.

endmodule

Why this shows up in interviews

UART Frame Assembler sits under Sequential Design (sequential, fsm, communication). Concept: A UART receiver idles with rx high and treats a falling edge as a start bit, then shifts in 8 bits LSB-first with rx_data <= {rx, rx_data[7:1]} (each new bit enters at the top and existing bits shift right, so the first bit received ends up in bit 0). After the 8th bit ( cnt==7 ), pulse rx_valid for one cycle and return to idle so the next start bit can be detected.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

FAQ