RTL Problems / Level 2 · Sequential Logic
What You Will Learn
By solving 4-Bit Up Counter — Sequential Counter, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Implement a 4-bit synchronous binary up-counter with active-low asynchronous reset (areset_n). The counter rolls over from 15 to 0.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Sequential logic, non-blocking assignments, bit vector addition.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
clk | input | 1 | Clock signal |
areset_n | input | 1 | Active-low asynchronous reset |
q | output | 4 | 4-bit counter value (0 to 15) |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Output increments by 1 on each rising clock edge when reset is inactive.
Synthesis Constraints: Unsigned 4-bit register arithmetic (`q <= q + 1'b1;`).
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Using integer variables instead of bit vectors, causing synthesis tools to infer 32-bit registers.', 'Adding blocking assignments in the counter loop.']
Silicon & Hardware Engineering Notes
FPGAs contain dedicated fast carry chains (such as CARRY4/CARRY8) optimized specifically for counter incrementers, achieving multi-hundred MHz performance.
Starter RTL Code
module top_module(
input clk,
input areset_n,
output reg [3:0] q
);
// 4-bit up counter with async reset
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input clk,
input areset_n,
output reg [3:0] q
);
always @(posedge clk or negedge areset_n) begin
if (!areset_n)
q <= 4'b0000;
else
q <= q + 1'b1;
end
endmodule
Related RTL Problems in Level 2
- D Flip-Flop — Positive-Edge-Triggered Storage — Implement a basic 1-bit positive-edge-triggered D flip-flop without reset.
- D Flip-Flop with Asynchronous Reset — Reset Behavior — Design a D flip-flop with active-low asynchronous reset (areset_n). Reset forces q to 0 immediately, independent of clk.
- D Flip-Flop with Synchronous Reset — Clocked Reset — Implement a D flip-flop with active-high synchronous reset (sync_rst). The reset takes effect only on the rising clock edge.
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Frequently Asked Questions
What does 4-Bit Up Counter — Sequential Counter require?
Implement a 4-bit synchronous binary up-counter with active-low asynchronous reset (areset_n). The counter rolls over from 15 to 0. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: sequential, fsm, counters, medium, counters. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of 4-Bit Up Counter — Sequential Counter to assess real-world synthesizability and race-condition awareness.