Weighted Round-Robin Arbiter

Verilog problems / Sequential Design

What you must build

Give one requester more grants per round than the other — the QoS-style arbiter behind bandwidth allocation in NoCs and shared-memory controllers.

Engineers use “Weighted Round-Robin Arbiter” as a building block in sequential design. Interviewers ask for the same ports and the same corner cases this judge covers. Completing it in the browser is the same skill as writing synthesizable RTL at work, minus the EDA license.

Port contract

The judge instantiates exactly these ports. Extra ports or a different module name fail to elaborate.

How to approach this kata

This is a hard kata. Sketch the state bits and the illegal overlaps (full/empty, wrap, simultaneous enable) on paper first. A design that “usually works” in your head will fail a directed corner in the hidden tests.

Hidden tests instantiate top_module, drive the ports, and compare every sample against a golden model. They do not grade coding style. They do grade X/Z, off-by-one counters, and ignoring enables. Sign in only when you want the run saved on the leaderboard — the specification below is public.

Starter shape

Copy this skeleton into the editor (or press Reset starter). Fill the body; do not rename the module.

module top_module(
  input  clk,
  input  rst,
  input  req0,
  input  req1,
  output reg grant0,
  output reg grant1
);

  // Your code here — W0=2, W1=1 quotas. Grant req0 while its quota lasts, then req1 while its quota
  // lasts (decrementing each grant), then refill both quotas once neither can be served.

Why this shows up in interviews

Weighted Round-Robin Arbiter sits under Sequential Design (sequential, arbiter). Concept: Each requester gets a quota of consecutive grants per round (here, 2 for requester 0, 1 for requester 1); a grant only counts against that requester's own quota, and the quotas refill together once neither requester can be served: if(req0 && q0!=0) begin grant0<=1; q0<=q0-1; end . Granting req0 unconditionally whenever it's asserted — without ever checking or spending its quota — throws the weighting away entirely: requester 0 wins every single cycle it asks, and requester 1 is starved completely instead of getting its fair 1-in-3 share.

A passing solution is synthesizable intent: no delays in the DUT, no initial blocks inside top_module, and no reference to testbench tasks. Use blocking assignments only in combinational always blocks; use non-blocking for registers clocked by clk.

Related problems

• D Flip-Flop with Asynchronous Reset — Standard D flip-flop with an active-low asynchronous reset. Reset clears q immediately, without waiting for a clock edge.
• 4-Bit Shift Register (SIPO) — Serial-in, parallel-out shift register. Each clock, shift left and load sin into the LSB. Sync active-high reset clears q.
• JK Flip-Flop — The flip-flop with no forbidden state: j=k=1 toggles instead of racing. Classic building block for counters.
• 4-Bit Up/Down Counter — A synchronous counter that increments or decrements each clock edge depending on a direction input, with a synchronous reset.

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