After placement locks every cell's location, routing must connect every pin with metal wires — navigating congestion, DRC rules, antenna effects, and signal integrity constraints to achieve zero-violation sign-off.
Global routing divides the die into a grid of GCells (global cells) and assigns each net to a sequence of GCells without specifying exact tracks. Its goal is congestion avoidance: routing demand in any GCell must not exceed the available routing supply (track count per layer). When demand exceeds supply, that GCell has overflow — a congestion hotspot that the detailed router cannot resolve.
Detailed routing takes the global routing guides and assigns each net to specific metal tracks and vias within each GCell. It must honor all DRC constraints (spacing, width, via enclosure) while completing every connection. The two most widely used detailed routing algorithms are:
| Stage | Resolution | Objective | Output |
|---|---|---|---|
| Global routing | GCell (5–15 µm) | Minimize congestion overflow | GCell routing guides per net |
| Track assignment | Metal track (0.04–0.1 µm) | Minimize via count, balance layers | Assigned tracks, via locations |
| Detailed routing | Single track / via | DRC-clean connections | Full routed layout (GDS shapes) |
| Search-and-repair | Per-net rip-up | Resolve remaining DRC violations | Zero-DRC routed design |
Modern ASIC processes stack 8–15 metal layers, each with a preferred routing direction that alternates to minimize coupling between adjacent layers. The stack is divided into three categories based on pitch and purpose:
| Layer group | Layers | Direction | Use | Pitch (7nm) |
|---|---|---|---|---|
| Local interconnect | M1, M2 | H / V alternating | Cell-to-cell connections, short nets | 28–36 nm |
| Semi-global | M3, M4 | V / H | Module-to-module, medium nets | 48–64 nm |
| Global | M5–M10 | H / V | Power/clock distribution, long wires | 80–160 nm |
| Ultra-thick | M9–M15 (AP) | Mixed | Power delivery, VDD/VSS planes | 400 nm–2 µm |
Every layer transition requires a via — a metal plug connecting two adjacent layers. Vias add both resistance (~5–20 Ω per via) and capacitance. For timing-critical nets, the router minimizes via count. For power nets, multiple vias in parallel ("via arrays") reduce resistance. Each via also consumes routing area, creating congestion in dense designs.
DRC verifies that the routed layout conforms to the foundry's physical design rules — the minimum geometric constraints required for reliable fabrication. A modern PDK may contain hundreds of DRC rules per metal layer.
| Rule type | Description | Effect of violation |
|---|---|---|
| Min spacing | Minimum gap between two wires on the same layer | Shorts during lithography/etch |
| Min width | Minimum metal wire width | High resistance, electromigration risk |
| Min enclosure | Via must be surrounded by metal on all sides by minimum amount | Via exposure, connection failure |
| End-of-line (EOL) | Extra spacing required at wire endpoints (jogs) | Shorts at line ends under lithography |
| Min area | Metal shape must have minimum total area | Metal island lost during etch |
| Parallel run length | Two parallel wires need wider spacing if they run alongside each other beyond a length threshold | Coupling, shorts |
The router runs iterative DRC-aware search-and-repair loops. Each iteration detects remaining violations and re-routes the smallest set of conflicting nets needed to resolve them. For a complex design, 5–10 repair passes are typical before achieving zero DRC violations.
# Run full routing (global + track assign + detailed) route_auto \ -max_routing_layer M8 \ -global_detail_route_effort high \ -track_assign_effort high # Check DRC after routing check_drc -output_directory ./drc_reports # Report routing congestion per layer report_routing_congestion \ -layer_range {M1 M8} \ -overflow_threshold 0.01 # Fix remaining DRC violations with ECO router route_eco -fix_drc -max_iterations 10
During semiconductor fabrication, plasma etching and deposition processes generate electric charge that accumulates on exposed metal. If a long wire is connected to a gate oxide (transistor gate) before it is connected to any other diffusion (drain/source), the accumulated charge has nowhere to go — it discharges through the thin gate oxide, permanently damaging or destroying the transistor.
The antenna ratio (also called the PAR — process antenna ratio) measures the risk:
Antenna Ratio = Metal Area (accumulated charge) / Gate Oxide Area
Each PDK specifies a maximum allowed antenna ratio per layer (typically 50–400). Violations must be fixed before tapeout. Two standard fixes exist:
Two adjacent parallel wires on the same metal layer form a parasitic capacitor. When the aggressor net switches (changes voltage), the capacitive coupling injects a noise spike onto the quiet victim net. This is crosstalk noise (or coupling noise).
| Effect | Description | Consequence |
|---|---|---|
| Crosstalk noise (glitch) | Coupling spike on a static victim net | Logic error if spike exceeds noise margin |
| Crosstalk delay (slow) | Aggressor switches in opposite direction to victim | Victim transition slowed — setup violation risk |
| Crosstalk delay (fast) | Aggressor switches same direction as victim | Victim transition faster — hold violation risk |
# Define NDR for clock nets (double width + spacing) create_routing_rule ndr_clock \ -default_reference_rule \ -widths {M3:0.072 M4:0.072 M5:0.100} \ -spacings {M3:0.072 M4:0.072 M5:0.100} # Apply NDR to clock net set_net_routing_rule -rule ndr_clock [get_nets clk*] # Shield clock nets with VDD/GND add_shield -net clk -shield_net VSS -layers {M3 M4}
Engineering Change Order (ECO) routing handles small netlist changes made after the design is fully routed — often after functional verification catches a bug or a timing ECO adds/moves cells. The goal is to fix the changed connections with the minimum perturbation to the existing routes (no full re-route).
ECO routing works in three steps: (1) identify changed nets from the ECO netlist delta, (2) rip up only those nets plus any conflicting neighbors, (3) re-route using the existing routing database, respecting all DRC rules. A good ECO affects fewer than 1% of nets. Large ECOs (> 5% of nets changed) may require a full re-route.