STA mathematically verifies that every data path in the chip meets timing — without running a single simulation. It is the gatekeeper between your routed design and the foundry, and the last step before sign-off.
📖 ~35 min read🎯 Setup · Hold · OCV · MCMM · ECO🏭 Next: Design for Test →
Every flip-flop has two fundamental timing requirements relative to its clock edge:
Setup time (T_su): Data must arrive and be stable at the D input at least T_su before the capturing clock edge. Violating setup causes the FF to sample the wrong value (metastability risk).
Hold time (T_h): Data must remain stable for at least T_h after the capturing clock edge. Violating hold similarly causes metastability.
For a single-cycle path from FF_A (launch FF) to FF_B (capture FF):
Data must arrive before capture clock edge minus T_su
Hold (min delay)
Slack = T_data + skew_launch − skew_capture − T_h
Data must stay valid until after capture clock edge plus T_h
Key insight: Setup and hold are checked at different clock edges. Setup is checked at the next capture edge (T_clk away). Hold is checked at the same capture edge as the launch edge — the data must hold through that edge even before it propagates further. Fixing setup requires slower paths or faster clocks; fixing hold requires faster paths (adding delay buffers).
2. Clock Domain Crossings in STA
When data travels from a flip-flop clocked by CLK_A to a flip-flop clocked by CLK_B (unrelated clocks), STA cannot compute meaningful setup/hold slack — the arrival and required times are in different time domains with no fixed phase relationship.
Standard approaches to handle CDC in STA:
set_false_path: Instructs STA to ignore timing on this path entirely. Used when the CDC is handled by a synchronizer (2-FF synchronizer, handshake, FIFO) that makes metastability risk negligible. False paths are excluded from all timing reports.
set_max_delay -datapath_only: Constrains the path to meet a specified delay budget (e.g., the synchronizer setup time) without requiring clock relationship analysis. More conservative than set_false_path.
create_clock -source_latency_included: For synchronous CDC (integer clock ratio), define both clocks with proper relationships so STA can analyze multicycle paths.
CDC is not fully caught by STA: STA with set_false_path tells you timing is "don't care" — it does not verify that your synchronizer design is correct. Use dedicated CDC analysis tools (Mentor Questa CDC, Synopsys SpyGlass CDC) to verify synchronizer topology, reconvergence, and data coherency.
3. On-Chip Variation (OCV)
Real chips have spatial variation in transistor threshold voltage, oxide thickness, and metal resistance — caused by lithography imperfections and chemical non-uniformity across the wafer. STA models this with On-Chip Variation (OCV) derating: apply a pessimistic multiplier to cell/wire delays.
AOCV (Advanced OCV)
AOCV applies distance-based derating. The further two points are apart on the die, the less likely they are to share the same process variation. Short paths get higher (more pessimistic) derating; long paths get lower derating. This reduces over-pessimism compared to flat OCV.
POCV (Parametric OCV)
POCV uses statistical derating — each cell's delay is modeled as a random variable with a mean and standard deviation. Paths are analyzed by propagating distributions (Monte Carlo or analytical), and slack is reported at a statistical confidence level (e.g., 3σ). POCV is the most accurate OCV model and is required for sub-5 nm sign-off.
OCV model
Derating approach
Accuracy
When used
Flat OCV
Single multiplier (e.g., 1.1× late, 0.9× early)
Most pessimistic
28 nm and older, or quick checks
AOCV
Distance + depth look-up table
Moderate
16–28 nm
POCV
Statistical distributions per cell
Most accurate
7 nm and below
4. MCMM — Multi-Corner Multi-Mode
A real chip operates under many conditions. MCMM analysis checks timing across all combinations of operating conditions (corners) and design modes simultaneously.
Modes
Functional mode: Normal operation. All logic paths active. Clock at target frequency.
Scan (test) mode: Scan chains shift in/out test data. Different clock topology, longer paths through scan mux.
Low-power mode: Some clock domains gated. Different activity factors, reduced frequency targets.
Corners
SS (Slow-Slow) / 0.9 V / 125°C: Worst-case for setup — slowest transistors, lowest voltage, highest temperature. Check setup here.
FF (Fast-Fast) / 1.1 V / −40°C: Worst-case for hold — fastest transistors, highest voltage, lowest temperature. Check hold here.
TT (Typical-Typical) / 1.0 V / 25°C: Nominal corner for power estimation and performance benchmarking.
Why does temperature affect timing the way it does? In CMOS, higher temperature increases carrier scattering, reducing MOSFET mobility and thus drive current. Lower drive current = slower switching. At advanced nodes (< 28 nm), this "temperature inversion" effect partially reverses — some cells are actually slower at lower temperatures due to threshold voltage increase. The STA tool must use the correct liberty files for each corner.
5. Timing ECO
After routing, if timing sign-off reveals violations, a timing ECO is performed to fix them without disturbing the rest of the design:
Cell upsizing: Replace a smaller drive strength cell with a larger one (e.g., BUF_X1 → BUF_X4). Increases drive current, reduces propagation delay on the critical path.
Buffer insertion: Split a high-fanout net to reduce capacitive load on the driver.
Logic restructuring: Flatten or rebalance a logic cone to reduce the longest path through it.
Useful skew (clock ECO): Adjust clock buffer sizing in the clock tree to intentionally skew the clock, buying setup margin on a specific path.
Hold fix (delay insertion): Insert delay cells (DELBUF) on the minimum-delay path to satisfy hold.
# Report timing: worst setup path, full clock detailsreport_timing \
-path_type full_clock \
-delay_type max \
-max_paths 20 \
-slack_lesser_than 0.1# Set OCV derating for late/early pathsset_timing_derate -late 1.08 -cell_delay
set_timing_derate -early 0.92 -cell_delay
# Create MCMM scenario (setup check at SS corner)create_scenario -name func_ss_setup \
-mode functional \
-corner ss_0p9v_125c \
-is_active_for_setup true \
-is_active_for_hold false
# Create hold scenario at FF cornercreate_scenario -name func_ff_hold \
-mode functional \
-corner ff_1p1v_m40c \
-is_active_for_setup false \
-is_active_for_hold true
6. Sign-Off Corners
Sign-off STA runs the full set of required corners to guarantee the chip works across all valid operating conditions:
Corner name
Condition
Check
Risk if violated
SS / 0.9V / 125°C
Slow process, low voltage, hot
Setup (max delay)
Functional failure at target frequency
FF / 1.1V / −40°C
Fast process, high voltage, cold
Hold (min delay)
Metastability, data corruption
TT / 1.0V / 25°C
Nominal
Setup + hold + power
Off-spec performance
SS / 0.9V / −40°C
Slow process, low voltage, cold
Setup (some nodes)
May be worst setup at sub-28 nm (temp inversion)
FF / 1.1V / 125°C
Fast process, high voltage, hot
Hold (some paths)
Hold at very short paths with fast driver
⏱ Interactive: Timing Path Analyzer
Adjust clock and path parameters. The tool computes setup and hold slack in real time and draws a timing diagram. Negative slack = violation (shown in red).
Clock period (ns)2.5
Clock uncertainty (ps)50
Clock skew (ps)30
Data path delay (ps)1800
Setup time (ps)60
Hold time (ps)30
SETUP CHECK
HOLD CHECK
✅ Chapter 7 Key Takeaways
Setup slack = clock period + capture_skew − launch_skew − data_delay − setup_time; must be ≥ 0
Hold slack = data_delay + launch_skew − capture_skew − hold_time; must be ≥ 0
CDC paths between unrelated clocks must use set_false_path or set_max_delay; verify synchronizer topology with CDC tools
POCV is required for sub-7 nm sign-off; it uses statistical distributions rather than flat multipliers
MCMM checks all mode/corner combinations: setup at SS/slow/hot, hold at FF/fast/cold
Timing ECO fixes (upsizing, buffering, useful skew, hold buffers) must be followed by full re-sign-off