Tapeout

1. What is Tapeout

Tapeout is the delivery of the final chip layout — a GDS2 (GDSII) file — to the semiconductor foundry. The name derives from the era when design data was physically delivered to the fab on magnetic tape. Today, the encrypted GDS2 database is transmitted electronically, but the moment remains the most significant milestone in the chip development process.

GDS2 format

GDS2 is a hierarchical binary database format that stores every geometric polygon on every mask layer of the chip. A modern SoC GDS2 file is typically 50–500 GB, containing trillions of polygons across 60–100 mask layers. The foundry uses the GDS2 file to generate photomasks — the glass reticles that expose the wafer during lithography.

Multi-Project Wafer (MPW) shuttles share a mask set across multiple designs, splitting the cost. Foundries (TSMC, GlobalFoundries) run regular MPW shuttles — small companies and universities can tapeout for a fraction of the full mask cost by sharing die space with other customers.

2. Physical Verification — DRC, LVS, ERC

DRC (Design Rule Check)

DRC verifies that every polygon in the GDS2 conforms to the foundry's manufacturing rules. A modern PDK contains thousands of DRC rules per layer — minimum spacing, minimum width, via enclosure, density rules, forbidden patterns, and complex multi-layer interaction rules. Sign-off DRC uses the foundry's official rule deck (not the EDA tool's internal rules) run on Calibre or PVS.

LVS (Layout vs Schematic)

LVS extracts the netlist from the GDS2 layout by tracing metal connectivity through vias and comparing it to the schematic (or post-route netlist). Every net, every transistor, every device parameter must match exactly. Common LVS failures:

• Open circuit: A via or contact is missing, breaking a connection present in the schematic
• Short circuit: Two nets connected in layout but not in schematic (often from a DRC spacing violation that became a short)
• Device mismatch: Transistor width/length extracted from GDS differs from the intended value
• Floating node: A net in the layout has no connection to any power or ground (antenna or floating gate risk)

ERC (Electrical Rule Check)

ERC catches electrical issues that DRC and LVS miss: floating gate inputs (undriven gates that may latch-up), antenna violations, ESD rule violations, and power domain connectivity errors. ERC complements LVS — where LVS checks connectivity structure, ERC checks electrical correctness.

3. Fill Insertion

Semiconductor manufacturing requires uniform metal and poly density across the die for CMP (Chemical Mechanical Planarization) — the polishing step that planarizes each layer. Where density is too low, CMP over-polishes, creating dishing and erosion. Where density is too high, CMP under-polishes, leaving bumps. Both affect the flatness of the next deposited layer, ultimately impacting yield.

The fill engine automatically inserts dummy fill shapes — floating metal or poly polygons with no electrical connection — to bring all layers within the foundry's density window (typically 20–80% density measured in any 50×50 µm window). Fill shapes are added after routing and before DRC sign-off, because they affect the final DRC density checks.

4. Seal Ring

The seal ring is a closed ring of metal and poly that runs around the entire chip perimeter, just inside the scribe line (the area where the wafer is diced). It serves two critical protection functions:

• Moisture and contamination barrier: The seal ring prevents moisture and contaminants from diffusing laterally into the chip from the diced edges. It must be a continuous loop of metal connected through vias on every layer from poly to the top metal.
• Mechanical protection: The saw blade applies stress during dicing. The seal ring's metal stack distributes this stress, preventing crack propagation into the active die area.

Inside the seal ring, an inner guard ring (often called an ESD guard ring) provides additional ESD protection. These guard rings use specific PDK cells and must connect to VDD and VSS rails. DRC checks that the seal ring is complete (no gaps) and that all via connections are present.

5. GDS Merge and Final Signoff

The final GDS2 is not a single file generated by the router — it is a merge of multiple components:

1. Standard cell GDS: From the cell library (provided by the foundry or IP vendor)
2. Macro GDS: Hard IP blocks (memory compilers, analog IP, PHYs) with their own GDS
3. IO pad GDS: Pad cells around the chip perimeter for wire bonding or flip-chip bumping
4. Fill GDS: Metal/poly fill shapes from the fill engine
5. Seal ring GDS: The perimeter protection ring

The merge tool (Calibre Merge, PVS Stream) hierarchically combines all components into a single master GDS. The final DRC and LVS must run on this merged GDS — not on intermediate pre-merge databases. Any differences between the merged GDS and the post-route database must be investigated and resolved.

# Run final DRC sign-off (Calibre)
run_drc \
  -rule_file ${PDK_DIR}/calibre_drc.rule \
  -layout_file final_chip.gds \
  -top_cell CHIP_TOP \
  -output_db ./signoff/drc_results.db

# Run LVS sign-off
run_lvs \
  -rule_file ${PDK_DIR}/calibre_lvs.rule \
  -layout_file final_chip.gds \
  -source_file final_netlist.cdl \
  -report ./signoff/lvs_report.txt

# Insert dummy fill
create_fill \
  -layers {M1 M2 M3 M4 M5} \
  -space_to_signal 0.1 \
  -density_window 50

# Export GDS stream for foundry
export_stream \
  -format GDS2 \
  -output final_chip_tapeout.gds \
  -map_file metal_layer_map.txt \
  -merge_files {cells.gds macros.gds pads.gds fill.gds sealring.gds}

6. First Silicon to Production

After the GDS2 is accepted by the foundry, the journey from digital file to working chip takes months:

1. Wafer fabrication (8–12 weeks): 300 mm silicon wafers go through 500–1500 process steps: lithography, deposition, etch, implant, CMP. Each step builds one layer of the chip. A modern 3 nm chip takes ~3 months to fabricate from blank wafer to finished wafer.
2. Wafer test (1–2 weeks): Electrical probing of each die on the wafer using a probe card. Failing dice are inked or mapped. Yield = passing die / total die.
3. Packaging (2–4 weeks): Wafer is diced into individual chips. Each chip is attached to a package substrate (BGA, TSOP, flip-chip), and connections are made by wire bonding (gold or copper wires) or flip-chip bumping (solder bumps on the chip face). The package protects the die and provides standardized I/O.
4. Chip bring-up: First packaged chips are powered on for the first time. Basic tests: power-on reset, supply current check, JTAG connectivity, PLL lock. Initial bring-up in a controlled lab environment with scope probes and JTAG debuggers.
5. Silicon characterization: Measure actual timing performance across PVT corners. Plot Fmax vs VDD curve. Compare to STA predictions. If worst-case is faster than predicted, relax speed bins. If slower, investigate timing failures — often a specific critical path or systematic process issue.
6. Production qualification: Stress tests for reliability: HTOL (High Temperature Operating Life: 125°C at nominal VDD for 1000 hours), ESD (electrostatic discharge), latch-up, thermal cycling. Parts that pass all qualification tests are approved for production shipment.