Power Analysis & Signoff

1. Power Components

Total chip power has two main components:

Dynamic power

Switching power is the dominant term: P_sw = α · C · V² · f, where α is the activity factor (fraction of clock cycles with a transition), C is total capacitance switched, V is supply voltage, and f is clock frequency. This is consumed each time a net switches, charging or discharging its capacitive load.

Short-circuit power occurs briefly when both PMOS and NMOS transistors are simultaneously conducting during a transition. It is typically 5–10% of switching power at older nodes but diminishes at advanced nodes with fast-switching transistors.

Static (leakage) power

Even when the circuit is not switching, current flows through transistors due to three mechanisms:

• Subthreshold leakage: The dominant term. MOSFET channel conducts weakly below V_th. Increases exponentially with temperature and inversely with V_th. At 7 nm, leakage can be 30–40% of total chip power at 125°C.
• Gate leakage: Current tunneling through ultra-thin gate oxide. Managed by using high-k dielectrics at 45 nm and below.
• Junction leakage: Reverse-biased p-n junctions leak current. Usually small.

2. IR Drop

The power delivery network (PDN) — VDD and VSS metal rings and straps — has finite resistance. When cells draw current (I), the resistive drop (V_drop = I × R_grid) reduces the effective supply voltage at the cell. IR drop degrades both performance (lower VDD = slower switching) and timing margin.

Static vs Dynamic IR drop

• Static IR drop: Computed from average current draw (DC analysis). V_drop = I_avg × R. Shows which regions of the die chronically receive lower voltage due to poor PDN connectivity.
• Dynamic IR drop: Caused by simultaneous switching events (e.g., many FFs capturing on the same clock edge). Peak current demand creates a transient voltage droop that can be much larger than static IR drop. Dynamic IR drop is worsened by parasitic inductance in the package (L·dI/dt).

3. Electromigration (EM)

Electromigration is the gradual displacement of metal atoms by momentum transfer from flowing electrons. Over time, metal atoms migrate in the current direction, creating voids (leading to opens) at the cathode and hillocks (leading to shorts) at the anode. EM causes chip failure years after deployment — a reliability concern, not a functional one at tapeout.

Black's equation

MTTF = A · J⁻ⁿ · e^{(Ea / kT)}

Where: J = current density (A/µm²), n = current density exponent (~2 for aluminum, ~1 for copper), Ea = activation energy (~0.7 eV for copper), k = Boltzmann constant, T = temperature in Kelvin. Every PDK specifies a maximum allowed current density J_max per wire width per layer. EM fixes: widen wire, add parallel wires, add more vias, reduce switching activity.

4. Power Domains and UPF

UPF (Unified Power Format) is the IEEE standard for specifying power intent. Modern SoCs partition the chip into multiple power domains (voltage islands) — different blocks operate at different voltages to save power.

Special cells at domain crossings

• Level shifters: Convert signals crossing voltage domain boundaries. A 0.7V signal driving a 1.0V receiver needs a level-up shifter to prevent the receiver from reading it as logic 0.
• Isolation cells: When a domain is power-gated (turned off), its outputs must be clamped to a known logic level so the receiving domain doesn't see floating inputs. Isolation cells clamp outputs based on the power-gate enable signal.
• Retention FFs: Standard FFs lose state when power-gated. Retention FFs have a shadow latch that can hold state during power-off and restore it when power returns.

# Report total power breakdown
report_power \
  -scenario func_ss_setup \
  -hierarchy \
  -verbose

# Analyze power rail for IR drop
analyze_power_rail \
  -rail_name VDD \
  -type static \
  -report ./reports/ir_drop.rpt

# UPF: Create power domain (Innovus)
create_power_domain -name PD_CPU \
  -elements {u_cpu}

# Define voltage area for domain
create_voltage_area -name VA_CPU \
  -power_domain PD_CPU \
  -coordinate {100 200 500 800}

5. Clock Gating

Clock gating is the most impactful dynamic power reduction technique available without changing the architecture. An ICG (Integrated Clock Gate) cell places a latch + AND gate in the clock path. When the enable signal is deasserted (block is idle), the clock to all FFs in that block is stopped — their switching power drops to zero.

ICG operation

The latch samples the enable signal on the clock's falling edge (when the AND gate output is forced 0 by the clock being low). This ensures the enable cannot create a glitch on the gated clock output, regardless of when the enable changes relative to the rising edge.

6. Power-Aware Physical Design

The power grid must be planned at the floorplan stage and refined through routing. Key considerations:

• Power strap sizing: VDD/VSS horizontal and vertical straps are sized by current density limit. A block drawing 500 mA needs straps wide enough that J < J_max at every point.
• VDD/VSS ring: A ring of metal surrounds the core area, connecting to the top-level supply. Ring width is determined by the total chip current.
• Decap cells: Decoupling capacitor cells placed near high-activity logic store charge locally. During simultaneous switching, decaps supply current immediately (before the distant power source responds), reducing dynamic IR drop and package inductance effects.
• Multiple power domains in floorplan: Voltage islands must be placed with level shifters at their boundaries. The floorplan must ensure isolation cells are accessible and that retention FF arrays can be powered from a separate, always-on supply rail.