Internal Flow
Inside the Synthesizer — 4 Phases
Phase 1
Elaboration — Building the Design Database
1
Read RTL Files
Tool reads all Verilog/VHDL files. Syntax and semantic checks run. Module definitions are registered in the tool database.
2
Elaborate Hierarchy
Top module is elaborated. Parameters are resolved (e.g., WIDTH=8). Generate loops are expanded. Each sub-module instance is linked to its definition.
3
Infer Flip-Flops & Latches
The tool recognizes sequential always blocks and infers DFFs, scan-FFs, or latches. Clock enable, reset polarity, and set/reset priority are determined from the RTL.
4
Build GTECH Network
RTL operators (+, *, >>, ?:) are mapped to GTECH primitives (GTECH_AND, GTECH_OR, GTECH_DFF, GTECH_MUX). This tech-independent network is then optimized.
## Design Compiler — Read & Elaborate set_app_var link_library "* my_stdcell.db" set_app_var target_library "my_stdcell.db" analyze -format verilog {top.v alu.v regfile.v} elaborate TOP -parameters "WIDTH=32" link check_design ## look for undriven nets, multiple drivers
## Cadence Genus — Read & Elaborate read_libs "my_stdcell.lib" read_hdl {top.v alu.v regfile.v} elaborate check_design -all
Phase 2
Generic Logic Optimization (GTECH)
Before touching any library cells, the tool optimizes the Boolean network in a technology-independent space. This produces a minimal logic structure that the tech mapper can then efficiently implement.
| Technique | What It Does | Effect |
|---|---|---|
| Boolean Simplification | Applies Karnaugh/Quine-McCluskey / BDD-based minimization to reduce logic cones | ↓ gate count, ↓ delay |
| Constant Propagation | Evaluates logic with tied-high/low signals at compile time and removes dead logic | ↓ area, removes X-propagation |
| Don't-Care Optimization | Uses unreachable states (SDC false paths) as don't-cares to simplify logic | ↓ area, ↓ power |
| Common Sub-expression | Identifies shared logic cones and merges them to share gates | ↓ area |
| Redundancy Removal | Removes redundant logic that doesn't affect observable outputs | ↓ area |
| Retiming | Moves flip-flops across combinational logic to balance pipeline stage delays | ↑ Fmax, balanced paths |
Phase 3
Technology Mapping — GTECH → Standard Cells
| Synthesis Output | File Format | Used By | Contains |
|---|---|---|---|
| Gate-Level Netlist | .v (Verilog) | P&R (Innovus/ICC2) | Instantiated std-cell connections |
| Timing Constraints | .sdc | P&R, STA | Clocks, I/O delays, false paths |
| Standard Delay Format | .sdf | Gate-level simulation | Cell & wire delays for sim |
| Timing Report | .rpt | Engineer review | WNS, TNS, critical paths |
| Area Report | .rpt | Engineer review | Cell count, total area (µm²) |
| Power Report | .rpt | Engineer review | Dynamic + leakage (µW/mW) |
Compile Commands
Design Compiler Compile Strategies
| Command | Effort | Runtime | When to Use |
|---|---|---|---|
compile | Medium | Fast | Early exploration, quick QoR check |
compile -inc | Medium | Fast | Incremental fixes after ECO changes |
compile_ultra | High | Slow | Final signoff synthesis, max timing QoR |
compile_ultra -retime | Highest | Slowest | Sequential optimization — move FFs across combo |
compile -map_effort medium | Controlled | Medium | Balance runtime vs QoR in large designs |
## Typical DC synthesis script source constraints.sdc # apply timing constraints compile_ultra -no_autoungroup # preserve hierarchy for P&R ## Reports report_timing -max_paths 10 report_area report_power report_constraint -all_violators # DRC: fanout, transition violations ## Write outputs write -format verilog -hierarchy -output netlist.v write_sdc top.sdc write_sdf top.sdf
## Cadence Genus — equivalent flow read_libs "stdcell_tt.lib" read_hdl {top.v sub.v} elaborate read_sdc "constraints.sdc" syn_gen # generic synthesis syn_map # technology mapping syn_opt # timing optimization report_timing write_hdl netlist.v write_sdc top.sdc
Pitfalls
Common RTL Issues That Hurt Synthesis
| Issue | Symptom in Synthesis | Fix |
|---|---|---|
| Combinational feedback / loops | Unreachable states, infinite loops, warning: combinational loop | Add registered stage or synchronous reset to break feedback |
| Unintended latches | Latch inferred from incomplete case/if — holds value, causes timing issues | Use default assignments at top of always block; use case with default |
| Multiple drivers | Multi-driver error on a net — undefined logic value | Ensure only one always block drives each net; use tri-state with enable |
| Very wide datapaths | 64b multipliers infer huge cells; long critical paths | Pipeline multiplier stages; use DesignWare components (dw_mult) |
| Gated clocks in RTL | Clock gating inferred incorrectly; DFT problems | Use ICG (Integrated Clock Gating) cells; set dont_touch on clock gates |
| Asynchronous resets across hierarchy | Reset trees inferred differently at each level | Use synchronous resets or dedicated reset synchronizer modules |
Interview Q&A
Top Questions — RTL to Netlist
What is GTECH and why does synthesis use it?
GTECH is Design Compiler's internal technology-independent gate library (GTECH_AND2, GTECH_OR2, GTECH_DFF, etc.). Synthesis first maps RTL to GTECH, optimizes the Boolean network without any library constraints, then maps the optimized network to actual standard cells. This two-phase approach allows more aggressive Boolean optimization before cell timing constraints are applied, yielding better QoR than mapping directly from RTL to library cells.
What is compile_ultra and what optimizations does it enable?
compile_ultra is DC's highest-effort synthesis command. It enables: (1) TDC — timing-driven compile with estimated placement; (2) datapath extraction — recognizes adder/multiplier patterns for DesignWare components; (3) register retiming — moves FFs across combinational logic; (4) constant propagation and dead-code removal; (5) logic duplication to fix high-fanout nets; (6) multi-pass incremental compile. It produces 10–20% better timing QoR vs plain compile at 3–10× longer runtime.
Why does post-route timing fail even though synthesis timing passed?
Synthesis uses wire-load models (WLM) — a statistical estimate of wire resistance/capacitance based only on fanout count. After P&R, actual RC extraction shows real wire delays which can be 2–5× higher than WLM estimates, especially for long nets crossing the die. Fix: (1) add synthesis timing margins (set_clock_uncertainty, OCV derate); (2) run physically-aware synthesis (DC-G, Genus iSpatial) using estimated placement; (3) close timing iteratively in P&R with ECO synthesis.
What does set_dont_touch do and when do you use it?
set_dont_touch prevents the synthesizer from optimizing, resizing, or removing a cell or net. Used on: scan flip-flops (DFT — ATPG must see exact flop type); clock tree buffers (CTS will resize these during P&R); black boxes (IPs with no RTL model); manually placed tie cells (tie-high/low at ports). set_dont_touch_network applies to all cells in the transitive fanout cone.
What is the difference between analyze and read_file in Design Compiler?
analyze -format verilog parses the file and stores it in the DC database without elaborating (no top-level design is created yet). It's suitable for reading multiple files before elaborating the top module. read_file -format verilog does both parse and elaborate in one step — simpler for single-module designs. The two-step analyze+elaborate flow is preferred for hierarchical designs so parameters can be resolved at elaborate time.
How does retiming improve timing in synthesis?
Retiming (compile_ultra -retime) moves flip-flops across combinational logic to balance pipeline stage delays. Example: if stage A has 1.2 ns path and stage B has 0.6 ns path in a 1 GHz design (1 ns period), retiming can move logic from A to B to balance both at 0.9 ns — both now meet timing. Retiming must preserve functional equivalence (same I/O behavior) and respects false-path and multicycle-path constraints.