Liberty Library
Standard Cell Library — Liberty (.lib) Structure
/* Liberty snippet — NAND2X1 cell */ cell (NAND2X1) { area : 1.32; cell_leakage_power : 0.8e-9; pin (A) { direction: input; capacitance: 1.2e-15; } pin (B) { direction: input; capacitance: 1.2e-15; } pin (ZN) { direction: output; function: "!(A * B)"; /* NAND2 Boolean function */ timing() { related_pin: "A"; timing_sense: negative_unate; /* NLDM table: rows=input_slew, cols=output_cap */ cell_rise(delay_template_7x7) { index_1 ("0.01, 0.05, 0.1, 0.2, 0.4, 0.8, 1.6"); /* slew ns */ index_2 ("0.001, 0.005, 0.01, 0.02, 0.04, 0.08, 0.16"); /* pF */ values ( "0.012, 0.018, 0.024, 0.036, 0.059, 0.108, 0.208", "0.030, 0.037, 0.044, 0.057, 0.081, 0.130, 0.232", ... ); } } } }
Cell Sizing
Drive Strength & Cell Sizing
| Drive Strength | Relative Area | Relative Speed | Max Fanout | Use Case |
|---|---|---|---|---|
| X1 (minimum) | 1.0× | 1.0× (baseline) | ~4–6 | Non-critical paths, low-fanout nets |
| X2 | 1.8× | ~1.5× | ~8–12 | Moderate fanout, slightly critical nets |
| X4 | 3.2× | ~2.5× | ~16–24 | High-fanout nets, timing-critical paths |
| X8 | 6.0× | ~4× | ~32–48 | Very high fanout, most critical paths |
| X12/X16 | 9–12× | ~6–8× | ~64+ | Clock buffers, extreme fanout (pre-CTS) |
Wire Delay
Wire-Load Models vs Extracted RC
The gap between WLM and extracted RC causes most post-route timing failures. Mitigation: physically-aware synthesis (DC-G / Genus iSpatial) uses trial placement to estimate real wire lengths, giving 30–50% better correlation to post-route timing at synthesis time.
Arithmetic Components
DesignWare Components
| DesignWare Cell | RTL Pattern Recognized | Advantage vs Generic |
|---|---|---|
| DW_add / DW_inc | a + b, a + 1 | Optimized carry-lookahead adder; 20–40% smaller/faster than NAND-mapped ripple carry |
| DW_mult | a * b | Booth-encoded multiplier; 30–50% fewer cells than synthesized Wallace tree |
| DW_cmp | a > b, a == b, a < b | Unified comparator shared across multiple conditions |
| DW_div / DW_rem | a / b, a % b | Non-restoring division; much smaller than RTL-inferred iterative divider |
| DW_shifter | a << b, a >> b (variable shift) | Barrel shifter with optimized mux-tree |
| DW_sqrt | Integer square root | Digit-recurrence algorithm; heavily optimized |
## Force use of DesignWare components in DC set_app_var synthetic_library "dw_foundation_ver.sldb" # DC automatically infers DW cells for RTL arithmetic # Verify after compile: report_design -designware # shows which DW cells were inferred ## Explicitly instantiate for guaranteed selection: # module my_mult (input [15:0] a, b, output [31:0] p); # DW_mult_uns #(.a_width(16),.b_width(16)) u_mult (.A(a),.B(b),.PRODUCT(p)); # endmodule
Interview Q&A
Technology Mapping Interview Questions
What is a Liberty file and what does it contain?
A Liberty (.lib) file is the timing/power characterization database for a standard cell library. For each cell it provides: cell area (µm²), leakage power, input pin capacitance, and NLDM (Non-Linear Delay Model) tables — 2D matrices giving cell delay and output transition time as a function of input slew (rows) and output load capacitance (columns). Sequential cells also have setup/hold/recovery/removal tables. The synthesizer reads Liberty to determine which cells meet timing and to estimate total power.
How does the technology mapper choose between NAND2X1 and NAND2X2?
The mapper uses dynamic programming over the NAND graph. For each node (gate), it evaluates all candidate cells from the Liberty library that implement the same Boolean function, computing the cost (timing slack, area) for each choice given the current fanout and input slew. X1 is chosen for non-critical paths to save area; X2 or larger is chosen when the additional drive strength is needed to meet timing (slack is negative or near zero). After initial mapping, incremental sizing passes upsize cells on the most timing-critical paths.
What is a wire-load model and why does it cause post-route timing failures?
A wire-load model estimates net capacitance from only the fanout count — a lookup table built from statistical averages of similar designs. The actual wire delay after routing depends on the physical wire length, which depends on placement. Long nets crossing the die can have 5–10× higher capacitance than the WLM estimate. The synthesizer sees a clean timing report (slack ≥ 0), but after routing the long wire adds delay that pushes the slack negative. Solution: physically-aware synthesis (DC-Graphical, Genus iSpatial) uses estimated placement during synthesis to compute better wire-length estimates.
What is SPEF and how is it used in sign-off STA?
SPEF (Standard Parasitic Exchange Format) contains the extracted RC parasitics of all nets after routing: net resistance (R, in Ohms) and capacitance (C, in Farads/pF) from the actual routed geometry, extracted using the foundry's RC extraction rules. The sign-off STA tool (PrimeTime, Tempus) reads the SPEF file and uses real wire delays (Elmore: 0.69×R×C) instead of WLM estimates for timing analysis. SPEF + Liberty + SDC + extracted netlist = accurate sign-off timing — this is the final check before tapeout.
When would you use set_dont_use in synthesis?
set_dont_use tells the synthesizer to never use specific cells from the library. Use cases: (1) cells that are problematic for DFT (complex flops without scan pins); (2) cells that the foundry marks as "not recommended for new designs" (NR cells); (3) very high-leakage cells that violate the power budget; (4) cells with known reliability issues (e.g., ULVT in an automotive-reliability design); (5) cells that DRC rules prohibit in certain metal layers (antenna-prone large cells). Unlike dont_touch, dont_use prevents the cell from being selected — it still exists in the library.