ARM Cortex-M3 Memory Architecture & Stack Inspector
The Cortex-M3 has a 4 GB contiguous memory space partitioned into standard architectural regions: Code (Flash), SRAM, Peripherals, and System Control Space (SCS). Below is the live memory matrix and stack inspection.
Code / Flash Space (0x00000000 – 0x1FFFFFFF)
Contains the Vector Table, Reset Handler, Thumb-2 instructions, and constant literal pools. Initial MSP value is located at 0x00000000, and Reset Vector is at 0x00000004.
SRAM Memory Space (0x20000000 – 0x3FFFFFFF)
On-chip volatile RAM. Contains static data, heap, and the execution stack. In this simulator, the default stack pointer resets to top of SRAM (0x20008000) and grows downwards toward 0x20000000.
Peripheral Space (0x40000000 – 0x5FFFFFFF)
Memory-mapped registers for I/O: GPIO Direction (0x40000000), GPIO Output ODR (0x40000004), GPIO Input IDR (0x40000008), and UART0 (0x40001000).
System Control Space (0xE0000000 – 0xFFFFFFFF)
Houses the processor core peripherals: SysTick timer (0xE000E010), NVIC registers (0xE000E100), System Control Block SCB (0xE000ED00), and MPU.
Cortex-M3 Hardware Exception Stack Frame (Auto-Stacking)
Upon taking an interrupt or exception, the hardware automatically pushes eight 32-bit registers onto the active stack in descending order:
xPSR
PC (Return)
LR
R12
R3
R2
R1
R0
Nested Vectored Interrupt Controller (NVIC) & Exception Matrix
The ARM Cortex-M3 NVIC provides low-latency, deterministic exception and interrupt handling. Below is the active Vector Table and NVIC control registers.
24-Bit SysTick Timer Peripheral Simulator
The Cortex-M3 includes an integrated 24-bit down-counter (SysTick) designed to generate periodic interrupts for real-time operating systems (RTOS tick) and software delay routines.
SysTick Control & Registers
Interactive SysTick Controller
Configure the timer reload value and test periodic interrupt firing:
24 Practical ARM Cortex-M3 Assembly Laboratory Experiments
Every experiment comes pre-loaded with verified Thumb-2 assembly source code, objective, step-by-step execution path, and virtual hardware peripheral mapping. Click any card to load the code directly into the IDE.
ARM Cortex-M3 Engineering Curriculum · 20 Core Modules
Systematic, university-level technical guides covering processor microarchitecture, bus systems, interrupt controllers, and assembly optimization.
Cortex-M3 Instruction Set Reference & Technical FAQs
Comprehensive reference guide to ARMv7-M Thumb and Thumb-2 instructions supported by the EcrioniX Studio execution engine.
Data Processing & Arithmetic
32-bit ALU operations updating or preserving APSR condition flags:
- MOV / MOVS Rd, #imm | Rm – Move 32-bit value (MOVS updates N, Z flags)
- ADD / ADDS Rd, Rn, #imm | Rm – Add with optional APSR flag update
- SUB / SUBS Rd, Rn, #imm | Rm – Subtract with borrow generation
- ADC / SBC Rd, Rn, Rm – Add / Subtract with Carry flag
- MUL / MULS Rd, Rn, Rm – 32-bit hardware multiplication
- AND, ORR, EOR, BIC – Bitwise logical AND, OR, XOR, Bit Clear
- MVN Rd, Rm – Move Bitwise NOT (one's complement)
- CMP / CMN Rn, #imm | Rm – Compare / Compare Negative
- TST Rn, Rm – Test bits (AND without storing result)
Shifts, Memory & Branching
Barrel shifter, Little-Endian memory access, and control flow:
- LSL / LSR / ASR / ROR – Logical/Arithmetic Shift & Rotate
- LDR / STR Rd, [Rn, #offset] – Load / Store 32-bit word
- LDRB / STRB Rd, [Rn, #offset] – Load / Store 8-bit unsigned byte
- LDRH / STRH Rd, [Rn, #offset] – Load / Store 16-bit unsigned halfword
- PUSH / POP {reglist} – Hardware stack push/pop via active SP
- B / BEQ / BNE / BGT / BLT – Unconditional & conditional branch
- BL label – Branch with Link (stores return in LR)
- BX Rm – Branch and Exchange (BX LR returns from subroutine)
- CBZ / CBNZ Rn, label – Compare and Branch on Zero / Non-Zero
Frequently Asked Questions (FAQs)
The ARM Cortex-M3 is a high-performance, low-cost 32-bit RISC microprocessor based on the ARMv7-M architecture. It features a 3-stage Harvard pipeline, unified memory architecture, integrated Nested Vectored Interrupt Controller (NVIC), hardware single-cycle multiply, hardware divide, and a 24-bit SysTick timer.
No. Unlike classic ARM cores (such as ARM7TDMI or ARM9), the Cortex-M3 core executes exclusively in Thumb state. It utilizes Thumb-2 technology, allowing high-density 16-bit instructions and high-throughput 32-bit instructions to intermix freely without mode-switching overhead.
Cortex-M3 provides two physical stack pointers banked under R13: the Main Stack Pointer (MSP) and the Process Stack Pointer (PSP). MSP is the default stack used on boot, during all exception and interrupt handlers, and by the OS kernel. PSP is used by application user threads in Thread mode to isolate user task stack faults from kernel space.
Upon taking an interrupt, Cortex-M3 automatically pushes eight 32-bit registers to the current stack: R0, R1, R2, R3, R12, LR, PC, and xPSR. The Link Register is loaded with a special EXC_RETURN code (e.g., 0xFFFFFFF9). On executing BX LR, the core detects this code and un-stacks all eight registers in hardware without software assembly intervention.
These are three views of the 32-bit Program Status Register (xPSR). APSR (Application PSR) holds ALU condition flags: N (Negative), Z (Zero), C (Carry), V (Overflow), and Q (Saturation). IPSR (Interrupt PSR) holds the currently active exception number (0 = Thread mode). EPSR (Execution PSR) holds the Thumb state bit (T=1) and If-Then (IT) execution state bits.
SysTick is a 24-bit down-counting system timer built directly into the processor core (0xE000E010). Because it is part of the standard ARMv7-M architecture rather than an external vendor peripheral, operating systems (like FreeRTOS or Zephyr) can provide portable task preemption ticks across all Cortex-M microcontrollers.
The Nested Vectored Interrupt Controller (NVIC) is tightly coupled with the Cortex-M3 core, supporting up to 240 external interrupts with configurable priorities. Tail-chaining is an optimization where, upon exiting an ISR when another interrupt is pending, the processor skips pop/push operations and switches directly to the next ISR in as few as 6 clock cycles.
Cortex-M3 defaults to little-endian byte ordering: the least significant byte (LSB) of a multi-byte word is stored at the lowest memory address. For example, 32-bit word 0x12345678 at address 0x20000000 places 0x78 at byte 0, 0x56 at byte 1, 0x34 at byte 2, and 0x12 at byte 3.
The IT instruction enables up to four consecutive instructions to execute conditionally based on APSR flags without branching. For example, 'ITE EQ' makes the first instruction execute if Z==1 (Then), and the second execute if Z==0 (Else), reducing branch misprediction penalties.
A HardFault (Vector 3) occurs when an unrecoverable error happens, such as executing an undefined instruction, branching to an address with bit 0 cleared (attempting ARM state), an unaligned load/store when alignment checking is enabled, accessing an unmapped memory bus address, or fault escalation when another fault handler fails.
Peripherals are mapped into standard 32-bit address space: GPIOA Direction register is at 0x40000000, Output Data (ODR) is at 0x40000004 (controlling virtual LEDs and 7-segment display), Input Data (IDR) is at 0x40000008 (reading DIP switches), and UART0 is at 0x40001000.
Yes. The simulator implements genuine ARMv7-M execution semantics and is specifically structured around university embedded systems curricula (e.g. Yiu, Valvano, Mazidi) covering Thumb-2 assembly, ALU operations, stack frames, SysTick delays, and NVIC interrupts.
In Thumb-2, 32-bit constants can be loaded using MOVW (load 16 bits into lower half) followed by MOVT (load 16 bits into upper half), or via the pseudo-instruction 'LDR Rd, =const' which loads the value from a PC-relative literal pool in Flash.
The 'S' suffix instructs the processor to update the APSR condition flags (N and Z based on the result, and C on shifts). 'MOV' performs the register transfer without altering any flags. In 16-bit Thumb, low-register moves (R0-R7) generally imply flag updates (MOVS).
Yes. The two-pass assembler, cycle execution engine, virtual hardware board, and memory subsystems are implemented in client-side JavaScript. No data is sent to external servers, and full functionality is preserved offline.