Cache Simulator — Hits, Misses, Mapping & AMAT
This free interactive cache simulator lets you configure a CPU cache — size, block size, associativity and replacement policy — then play an address stream through it and watch exactly what happens: which set each address maps to, whether it is a hit or miss, which line gets evicted, and how the hit rate and AMAT evolve. It's built for computer-architecture students and anyone preparing for systems interviews.
How an address maps into the cache
Every memory address is split into three fields:
- Block offset =
log2(block size)low bits — selects the byte within a block. - Set index =
log2(number of sets)middle bits — selects which set to search. - Tag = the remaining upper bits — stored in the line and compared to detect a hit.
Number of sets = (cache size ÷ block size) ÷ associativity. The simulator shows this geometry live and colour-codes the tag / index / offset split of the current address.
Direct-mapped vs set-associative vs fully associative
- Direct-mapped (1-way) — one line per set; a block has exactly one home. Fast, but prone to conflict misses.
- N-way set-associative — N lines per set; fewer conflicts at the cost of an N-way tag compare.
- Fully associative — a single set; a block can live anywhere. Fewest conflict misses, most expensive lookup.
The 3 C's of cache misses
- Compulsory (cold) — first ever reference to a block; unavoidable. The log marks these in amber.
- Capacity — the working set is larger than the cache.
- Conflict — too many active blocks map to the same set and keep evicting one another (only in direct-mapped / set-associative).
AMAT — average memory access time
AMAT = hit time + miss rate × miss penalty. Lower associativity or smaller caches raise the miss rate and therefore AMAT. Try the same address stream with different associativities and watch AMAT change.
FAQ
What replacement policies are supported?
LRU (least-recently-used) and FIFO (first-in-first-out). LRU updates a line's recency on every hit; FIFO evicts the oldest-loaded line regardless of use.
What address format can I enter?
Hex (e.g. 0x1A or 1A) or decimal — separate addresses with spaces, commas or new lines.
Want to design the logic instead?
Try the Logic Gate Simulator and FSM Designer for building the digital circuits behind the memory system.
Related: Digital Electronics · FSM Designer · VLSI