What state encodings are supported?

Binary (minimum flip-flops), one-hot (one flip-flop per state, fastest next-state logic, common on FPGAs) and gray (adjacent states differ by one bit). The generated localparams change accordingly while the rest of the RTL stays the same.

Is the generated Verilog synthesizable?

Yes. The tool emits the standard three-process FSM template: a synchronous state register, a combinational next-state block, and a combinational output block with safe defaults. It works with Vivado, Quartus, Yosys and Synopsys DC.

How do I draw the state machine?

Use Add State to place states, mark one as the reset state, then use Add Transition to connect them and type the condition (a Verilog boolean on your inputs). Select any state or transition to edit its name, condition and output assignments in the inspector. The Verilog regenerates live.

FSM Designer — Convert a State Diagram to Verilog RTL

Q: What is the difference between a Moore and a Mealy state machine?

In a Moore machine the outputs depend only on the current state, so they are glitch-free and registered-friendly. In a Mealy machine the outputs depend on the current state AND the current inputs, which can react one cycle earlier but may produce combinational glitches. This tool generates both styles from the same diagram.

This free online FSM designer turns a drawn finite state machine into clean, synthesizable Verilog RTL. Place states on the canvas, connect them with transitions, type the conditions on your inputs, and the tool generates the standard three-process state-machine template live — no install, no signup. It supports both Moore and Mealy machines and binary, one-hot and gray state encoding, making it useful for digital design students, FPGA developers and RTL/verification engineers.

Moore vs Mealy state machines

Moore machine

Outputs depend only on the current state. Outputs are stable for the whole clock cycle and are glitch-free, which makes Moore machines easier to time and verify. They may need one extra state/cycle to react.

Mealy machine

Outputs depend on the current state and the current inputs. Mealy machines react one cycle earlier and often need fewer states, but their combinational outputs can glitch and need care at clock-domain boundaries.

This tool generates both from the same diagram — switch the output type and the output logic block restructures automatically (per-state for Moore, per-transition for Mealy).

State encoding: binary, one-hot and gray

Binary — uses the minimum number of flip-flops (ceil(log2(N))). Smallest area; more next-state logic.
One-hot — one flip-flop per state, only one bit set at a time. Simplest, fastest next-state logic and the usual choice on FPGAs where flip-flops are plentiful.
Gray — adjacent states differ by a single bit, reducing switching and useful where the state value crosses a boundary.

Pick the encoding with one click — only the localparam definitions change; the rest of the RTL stays identical.

The generated RTL: a clean 3-process FSM template

The tool emits the textbook coding style that synthesises predictably on Vivado, Quartus, Yosys and Synopsys Design Compiler:

A synchronous state register with selectable async/sync and active-high/low reset.
A combinational next-state block — a case on the current state with if / else if branches built from your transition conditions, and a safe default.
A combinational output block with every output defaulted to 0 first (so you never accidentally infer a latch).

How to use the FSM designer

Add State — click on the canvas to drop a state; rename it in the inspector.
Mark one state as the reset / initial state (shown with a double ring and reset arrow).
Add Transition — click the source state, then the target; type the condition such as start & ~done.
Set Moore outputs per state, or Mealy outputs per transition, in the inspector.
Copy the Verilog or download the .v file.

Example state machines to try

Classic FSMs that make great practice — build them and watch the RTL update:

Sequence detector (e.g. detect 1011) — the canonical Moore vs Mealy comparison.
Traffic-light controller — a timed Moore machine with green/yellow/red states.
Vending machine — accumulate coins and dispense, a classic textbook FSM.
UART / SPI control FSM — IDLE → START → DATA → STOP style sequencing.

Frequently asked questions

What does this FSM tool generate?

Synthesizable Verilog RTL using the standard three-process template — a clocked state register, a combinational next-state case, and a combinational output block with safe defaults.

Is the Verilog synthesizable?

Yes. It uses only synthesizable constructs and works with Vivado, Quartus, Yosys and Synopsys DC. The output block defaults every output to 0 to avoid latch inference.

Can it do both Moore and Mealy?

Yes — switch the output type and the output logic regenerates: per-state assignments for Moore, per-transition assignments (gated by the input condition) for Mealy.

Which state encoding should I use?

Binary for minimum area, one-hot for fastest logic on FPGAs, gray when single-bit transitions matter. You can switch instantly and compare the generated localparams.