Tune data rate, jitter, channel loss, noise, and pre-emphasis. Watch the eye open and close in real time. Every parameter you adjust is what PCIe, DDR, and USB engineers fight every day in the lab.
An eye diagram — also called an eye pattern — is the single most informative measurement a signal integrity engineer can make on a high-speed digital link. It is created by a digital oscilloscope operating in infinite persistence mode. The oscilloscope captures hundreds of thousands of consecutive bit periods, triggers on the data clock or a recovered clock, and overlays every 2-bit-period slice on the same X axis. The result looks like an open eye — or, when the signal degrades, a nearly closed one.
The eye is not a single waveform. It is a two-dimensional density histogram. Every point on the display represents how often the signal passed through that voltage at that time. Dense regions (where traces pile up) glow brightest. The open region in the center — where no signal ever appears — is the eye opening. That opening is what guarantees reliable bit detection. This lab simulates that exact process: it generates a PRBS-7 (pseudo-random binary sequence) bit stream, applies channel effects and noise, then folds every 2-UI window on top of each other to build the histogram you see on the canvas.
Eye diagrams are used every time an engineer designs a PCIe link, DDR5 memory channel, USB4 cable, 100 Gigabit Ethernet connection, or any SERDES interface above roughly 1 Gbps. Below about 100 Mbps, channels are clean enough that a simple oscilloscope probe suffices. Above 1 Gbps, the eye diagram is mandatory — without it, you cannot know whether the signal will meet its bit error rate budget at the far end.
Six numbers define an eye diagram completely. Each corresponds to a physical mechanism degrading the signal:
| Measurement | Definition | What Closes It | Typical Limit |
|---|---|---|---|
| Eye Height | Vertical gap between the '1' and '0' signal distributions at the center of the UI | Noise, ISI, power-supply ripple | > 150–300 mV for most SERDES |
| Eye Width | Horizontal gap free of signal traces at the decision threshold (mid-level) | Jitter — both random and deterministic | > 0.6–0.75 UI for most standards |
| Crossing % | Voltage of zero-crossings as a fraction of signal swing — ideally 50% | Duty-cycle distortion, threshold offset | 40–60% for most NRZ |
| Q Factor | (μ₁ − μ₀) / (σ₁ + σ₀) — separation of signal levels relative to noise spread | Noise, ISI both reduce this | > 6–7 for BER < 10⁻¹² |
| Jitter (RMS) | Standard deviation of zero-crossing timing | Clock noise, reference SSC, crosstalk | < 1–5 ps RMS for 25+ Gbps |
| Rise / Fall Time | 10–90% transition time of the eye's upper/lower traces | Channel bandwidth, driver slew rate | < 0.2–0.35 UI for NRZ |
The decision point — where the receiver samples the bit — is ideally at the exact center of the eye, both horizontally (center of the UI) and vertically (midpoint between signal levels). Any deviation from this point increases the probability of a wrong decision. A well-designed CDR (Clock and Data Recovery) circuit continuously adjusts this sampling point to stay inside the eye.
Key insight: Eye height and eye width are independent axes. A jittery channel can have a wide-open vertical eye (good noise margin) but a severely closed horizontal eye (timing margin gone). Noise closes the eye top-to-bottom. Jitter closes it left-to-right. ISI closes it in all directions simultaneously. You need both margins to guarantee reliable communication.
Inter-Symbol Interference (ISI) is the dominant source of eye closure above 5 Gbps. Every real transmission channel — PCB trace, connector, cable, via, solder joint — behaves as a low-pass filter. It attenuates high frequencies more than low frequencies. The skin effect causes resistance to rise with frequency. Dielectric loss converts signal energy to heat proportional to frequency squared.
The consequence is straightforward but devastating: a sharp bit transition contains high-frequency energy. The channel rounds that edge. The tail of the rounded transition bleeds into the next bit period, and the bit after that, and the bit after that. A long run of 1s charges the channel to nearly the full "1" level. When a 0 finally arrives, the residual charge from all those preceding 1s pulls the 0 voltage upward — making it look more like a 1. The decision circuit sees a degraded signal.
Channel insertion loss is measured in decibels at the Nyquist frequency (half the data rate). A 5 Gbps NRZ link has a Nyquist frequency of 2.5 GHz. A PCB trace of FR4 material loses approximately 1 dB per inch at 2.5 GHz. A 12-inch trace from CPU to DIMM slot can have 12 dB of insertion loss at Nyquist — enough to completely close the eye without equalization.
Insertion loss per inch of FR4 trace at 2.5 GHz Nyquist (5 Gbps NRZ)
Typical connector loss at 16 GHz (PCIe Gen5 Nyquist). Backplane connectors worse.
Total channel budget for PCIe Gen5 long reach — drives the need for DFE equalization
Maximum channel loss handled by 112G PAM4 links in 400GbE with full Tx+Rx equalization
In this lab, the Channel Loss slider controls the alpha coefficient of a first-order IIR low-pass filter applied to the bit stream before it is rendered. At 0 dB, every transition is sharp and the eye is wide open. At 15 dB, transitions are heavily rounded and ISI from previous bits visibly bleeds into each new bit period. You can see the eye close from the outside in — the center of the UI stays cleanest because ISI has had time to partially settle, while the edges of the UI show the blurred transitions overlapping.
Jitter is timing uncertainty — variation in the exact moment a signal crosses the receiver's decision threshold. If the ideal crossing occurs at time T₀, jitter means the actual crossing occurs at T₀ ± Δt, where Δt varies from bit to bit. Jitter is the primary mechanism that closes the eye horizontally.
Jitter specifications are always given at a target BER because RJ is Gaussian and unbounded. PCIe Gen5 specifies a total jitter budget of 70 ps peak-to-peak at BER = 10⁻¹². Increasing the Jitter slider in this lab adds Gaussian random jitter — watch the crossing region thicken and the horizontal eye opening shrink.
While jitter closes the eye horizontally, noise closes it vertically. Noise appears as random variations in signal amplitude, independent of timing. Sources include thermal noise (Johnson noise from resistances), shot noise (from current flow across junctions), power supply coupling, and electromagnetic interference from adjacent switching signals.
The Noise slider adds Gaussian-distributed amplitude noise to each sample of the waveform. At low noise levels, the '1' and '0' level bands are tight and well-separated — the eye is tall. As noise increases, both bands broaden and the eye height shrinks. When noise is large enough that the '1' band and the '0' band start to overlap at the decision threshold, the BER becomes catastrophically high.
The relationship between noise and BER is captured by the Q factor. Q = eye_height / (2 · σ_noise), and BER ≈ erfc(Q/√2) / 2. This is why the measurements panel shows both Q and estimated BER together — they are two views of the same underlying noise margin. A Q of 6 gives BER ≈ 10⁻⁹. A Q of 7 gives BER ≈ 10⁻¹².
Pre-emphasis (or transmitter de-emphasis) is the most widely used technique to compensate for channel ISI before the signal even enters the channel. The principle is elegant: since the channel attenuates high-frequency transition energy, the transmitter intentionally boosts transitions and de-emphasizes continuous-level bits.
A standard SerDes transmitter with 3.5 dB de-emphasis works like this: a bit that transitions from the previous bit is transmitted at full swing (e.g., 1000 mV differential). A bit that continues at the same level — a "post-cursor" — is transmitted at de-emphasized amplitude (e.g., 670 mV). The channel then applies its low-pass effect. At the receiver, the de-emphasized bits have been boosted by the ISI tail from the previous transition, and the continuous bits arrive at nearly the correct level. The eye opens.
In this lab, toggling Pre-Emphasis applies a simple de-emphasis model: bits that continue the same level after a transition have their amplitude reduced to 65% for the middle portion of the bit period. Apply heavy channel loss (10+ dB), then toggle Pre-Emphasis on and off — watch the eye reopen. This is exactly what a PCIe or USB SerDes does in silicon, configured via register writes to the PHY.
Beyond transmitter pre-emphasis, modern high-speed links use receiver equalizers: CTLE (Continuous-Time Linear Equalizer) boosts high frequencies to invert the channel's low-pass response. DFE (Decision Feedback Equalizer) uses previously decided bits to cancel the ISI tail of known history. These are not modeled in this lab but are essential at 25 Gbps and above. PCIe Gen5 mandates CTLE + 8-tap DFE in the receiver to handle channels up to 20 dB of loss at Nyquist.
Every major high-speed digital standard defines eye diagram compliance requirements. These are captured as a compliance mask — a forbidden zone on the eye diagram. If any portion of the oscilloscope's signal trace hits inside the mask during a compliance test, the device fails certification.
| Standard | Data Rate | Encoding | Min Eye Height | Total Jitter Budget |
|---|---|---|---|---|
| PCIe Gen3 | 8 GT/s | NRZ 128b/130b | 15 mV (after eq.) | ~200 ps @ BER 10⁻¹² |
| PCIe Gen5 | 32 GT/s | NRZ 128b/130b | 12 mV (after eq.) | 70 ps @ BER 10⁻¹² |
| PCIe Gen6 | 64 GT/s | PAM4 1b/1b FLIT | PAM4 3-level eye | 30 ps @ BER 10⁻⁶ (FEC) |
| USB4 Gen3×2 | 40 Gbps | NRZ 128b/132b | 16 mV (after eq.) | 30 ps RMS |
| DDR5-6400 | 6.4 GT/s | NRZ (no 8b10b) | 110 mV | 250 ps p-p |
| 100GBASE-KR4 | 25.78 Gbps/lane | NRZ 64b/66b | 40 mV | 30 ps RMS |
| 400G PAM4 | 53.125 Gbaud | PAM4 (2 bits/symbol) | 3 inner eyes | ~10 ps RMS |
Note how requirements tighten dramatically with data rate. DDR5 at 6.4 GT/s has a 250 ps jitter budget — a luxury compared to 100G Ethernet at 30 ps RMS for signals running four times faster. PCIe Gen6's switch to PAM4 (4-level signaling, 3 inner eyes) allowed doubling the data rate without doubling the bandwidth, at the cost of significantly reduced noise margin per eye and the need for Forward Error Correction (FEC).
During compliance testing, a standard-defined mask is loaded into the oscilloscope. The mask is a polygon — typically a hexagon or rectangle — that defines the minimum acceptable eye opening. The oscilloscope runs in infinite persistence mode, capturing millions of bit transitions. Any trace that enters the mask region is flagged as a mask violation. The number of violations divided by total samples gives a hit rate, which must be lower than the target BER.
For high-BER targets like PCIe (10⁻¹²), direct mask testing would require observing 10¹² bits — physically impossible in real time. Instead, testing uses statistical extrapolation: bathtub curves are measured (BER vs. sampling offset), and the curve is extrapolated to the target BER. The eye width at BER = 10⁻¹² is read from the extrapolated bathtub. This is why high-end oscilloscopes like Keysight Infiniium or Tektronix DPO cost tens of thousands of dollars — the analysis software and calibration are the real value, not the analog hardware.
Engineer's rule of thumb: Add 50 ps of timing margin and 100 mV of voltage margin to your eye diagram numbers before declaring a link compliant. Real systems have temperature variation, aging, power-supply noise, and manufacturing spread that all consume margin that looks absent in a lab measurement on a perfect board at room temperature.