Watch parallel data get squeezed onto one high-speed lane and rebuilt at the other end — animated, step by step. Then explore the eye diagram and the full TX/RX architecture.
One wide parallel word (left) is shifted out one bit per fast serial clock, travels the differential lane, and is shifted back into a parallel word (right). That speed multiplier is the whole point of SerDes.
Overlaying many bit periods reveals link quality. A wide-open eye = clean signaling with margin; a closed eye = bit errors. The receiver samples each bit at the centre of the eye.
Chips need to move staggering amounts of data — gigabytes per second — between each other and across boards. The obvious approach is a wide parallel bus: 32 or 64 wires, one bit each, all clocked together. It works at low speed, but at high speed it falls apart:
The fix is counter-intuitive: send the data one bit at a time on a single lane — but clock that lane extremely fast. That is exactly what SerDes (Serializer/Deserializer) does. Fewer wires, no inter-bit skew, far higher total bandwidth. It's why PCIe, USB, SATA, Ethernet, HDMI/DisplayPort and chiplet links (UCIe) are all serial.
A SerDes link has a transmit side and a receive side, mirror images of each other:
Here's a question the animation hides: if there's no clock wire, how does the receiver know when to sample each bit? The answer is CDR. A phase-locked loop at the receiver watches the transitions in the incoming data and locks its own oscillator to them, generating a clock perfectly aligned to the bit stream. It then samples each bit at the centre of the eye — the safest point, farthest from the noisy edges.
But CDR needs regular transitions to stay locked. A long run of identical bits (say 64 zeros) gives it nothing to track and it drifts. That's where line coding comes in.
8b/10b encoding maps every 8 data bits to a 10-bit symbol. Those two extra bits buy three things:
The price is 25% overhead (10 bits sent per 8 useful). Newer high-speed standards cut that with wider codes:
| Code | Overhead | Used by |
|---|---|---|
| 8b/10b | 25% | PCIe 1–2, USB 3.0, SATA, GbE |
| 64b/66b | ~3% | 10G+ Ethernet |
| 128b/130b | ~1.5% | PCIe 3.0+ |
Toggle the lab to 10-bit mode to picture the 8→10 expansion: more bits on the wire per data byte, but a rock-solid recovered clock.
SerDes lanes are differential — two wires (D+ and D−) carrying opposite versions of the signal. The receiver looks at the difference, which cancels common-mode noise picked up equally by both wires and allows tiny, fast, low-power swings. This is what makes multi-gigabit signaling over a cheap cable possible.
To judge whether a link will actually work, engineers use the eye diagram (the second lab above). Overlay thousands of bit periods and a clean signal forms a wide-open "eye." Noise, jitter (timing wobble) and inter-symbol interference (smearing from the channel) shrink the opening. A closed eye means bit errors. Drag the noise slider and watch the eye — and the link's reliability — collapse.
A parallel bus is 64 slow side-streets where all the cars must arrive at the same instant — impossible to coordinate at speed. SerDes is one expressway where cars travel single-file but extremely fast. Fewer roads, no coordination problem, far more throughput. The eye diagram is the traffic camera that tells you the expressway is safe to drive.
SerDes turns a wide parallel word into one ultra-fast serial bit-stream on a differential lane (TX: encode → PISO serialize → drive) and rebuilds it at the other end (RX: CDR recover clock → SIPO deserialize → decode). Line codes like 8b/10b keep enough transitions for the CDR and keep the link DC-balanced. The eye diagram tells you whether the high-speed signal is clean enough to recover without errors.
A Serializer/Deserializer pair that converts parallel data to a high-speed serial lane and back, moving huge bandwidth over very few wires.
At high speed, parallel buses suffer skew, crosstalk and huge pin counts; one fast serial lane removes inter-bit skew and boosts total bandwidth.
Clock-Data Recovery — the receiver extracts a sampling clock from the data's transitions, so no separate clock wire is needed.
Many bit periods overlaid; the open "eye" shows signal quality and margin. A closed eye means jitter/noise will cause bit errors.
A line code mapping 8 data bits to a 10-bit symbol for guaranteed transitions and DC balance, at 25% overhead.
Related: PCIe · All protocols · Eye Diagram tool · Scrambler Lab · All tools →