Two's Complement — and How an Adder Subtracts

RISC-V, ARM and x86 all store signed integers in two's complement. That is not a fashion. It is the encoding that lets one n-bit adder compute both A + B and A − B with almost no extra delay. This page is the public, school-to-interview version: why not ones' complement, and why there is no separate “subtractor arithmetic” in a typical ALU.

1. Unsigned bits cannot mean “minus”

Four bits can name 16 patterns. If you treat them as unsigned, they mean 0 through 15. To also mean negative integers you must reuse some of those patterns. The encoding is a contract: everyone (compiler, ALU, human) agrees what 1111 means.

Three historical contracts:

• Sign-magnitude — MSB is a sign flag; the rest is the absolute value. Two zeros (0000 and 1000 in 4-bit). Adders need a separate sign path. IEEE 754 floats still use a sign bit this way; integer ALUs generally do not.
• Ones' complement — negative = bitwise NOT. Two zeros again. Addition needs a correction.
• Two's complement — negative = NOT, then add 1. One zero. Addition needs no correction. This is what integer hardware kept.

2. Ones' complement: flip the bits

To form −N, invert every bit of N. In 4-bit, 3 is 0011, so −3 is 1100.

The trap is zero. Inverting 0000 gives 1111. Both are “zero”: +0 and −0. Comparators, beqz-style branches, and “is this register empty?” now have two answers for nothing.

Addition is also messy. If A + B produces a carry-out of 1, you must add that 1 back into the sum (end-around carry). That is a second add on the critical path — or extra muxing around the same adder.

3. Two's complement: flip, then add 1

−N = bitwise NOT of N, then +1. 4-bit 3: ~0011 = 1100, plus 1 = 1101. That pattern is −3.

Why +1? Mathematically you want N + (−N) = 2n, which looks like 0000 plus a carry out of the top bit. Ones' complement sums to 1111 (all ones = −0), not a clean wrap. The extra +1 slides the negative half so there is only one zero.

n-bit two's complement range is −2ⁿ⁻¹ … +2ⁿ⁻¹−1. Four bits: −8 to +7. The extra negative is real; 1000 has no positive partner. That is not a bug — it is the leftover code-point after you refuse to spend one pattern on a second zero.

4. Why 2's won

• One zero. Test-for-zero is “are all bits 0?” not “all 0 or all 1?”
• One adder. Signed add is the same circuit as unsigned add. No end-around carry.
• Subtract is add. Next section. This is the industrial reason.
• Sign bit still works as a glance. MSB = 1 means negative, same as the other encodings — but you do not need a separate signed adder.

Ones' complement is not “wrong maths.” It is worse silicon for a general-purpose integer ALU. That is the honest sentence.

5. There is no subtractor — you add

A standard-cell library may contain adder macros. The ALU does not need a second arithmetic block that “does minus.” For two's complement:

One control bit named sub can do both jobs: XOR every bit of B with sub (so sub=1 inverts), and drive cin from the same sub.

Paper check: 7 − 3

A = 0111, B = 0011. Invert B → 1100. cin = 1.

0111 + 1100 + 1 = 1_0100. Keep the low four bits: 0100 = 4. The leading 1 is the wrap carry; you do not add it back in (that would be ones' complement).

If you invert B and leave cin = 0, you compute A + ~B = A − B − 1 (here: 3). That is the classic student bug: you built a ones'-style invert and forgot the two's +1.

Same adder, 5 + (−3)

−3 is already 1101 in 4-bit two's. 0101 + 1101 = 1_0010 → 0010 = +2. No extra end-around. Compare to the 1's example above: same answer, one less add.

6. Verilog: synthesis infers this

Writing a - b is fine. The synthesizer builds invert + cin. If you instantiate only an adder, you still subtract by feeding it ~b and cin=1. Compact form:

module addsub #(parameter N = 4) (
  input  wire [N-1:0] a,
  input  wire [N-1:0] b,
  input  wire         sub,   // 0 = add, 1 = subtract
  output wire [N-1:0] y,
  output wire         cout
);
  // sub=1 → XOR inverts b, and cin is 1  →  y = a + (~b) + 1 = a - b
  assign {cout, y} = a + (b ^ {N{sub}}) + sub;
endmodule

This is combinational teaching RTL. A real CPU ALU still uses this idea; it may pipeline, flag overflow separately, and share the adder with address calculation. The identity does not change.

7. Do not confuse Cout with signed overflow

Unsigned add: Cout = 1 means the true sum did not fit in n bits.

Unsigned subtract: Cout is often treated as a borrow (polarity depends on how you defined cin; be consistent with your textbook).

Signed two's overflow is different: two positives added to a negative result, or two negatives to a positive. Hardware: carry into the MSB XOR carry out of the MSB. Wiring overflow = cout for signed subtract is a common interview fail.

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