Embedded test engines, March algorithms, and fault models — then run an interactive March C- simulation to watch stuck-at faults get caught live.
Memories occupy 70–80% of SoC area. Scan chains test logic flip-flops — they can't efficiently access the 2D array of bitcells inside a SRAM. MBIST places a compact FSM controller adjacent to each memory, running March algorithms at-speed without external ATE.
Fig 1 — MBIST architecture. The controller generates addresses + data patterns, drives them through the MUX into the memory, reads back the result, and compares it in the Response Analyzer. Any mismatch latches the failing address.
Different manufacturing defects create different electrical faults. Each fault model requires a specific test algorithm to guarantee detection.
| Fault | Symbol | Behavior | Root Cause | Detected By |
|---|---|---|---|---|
| Stuck-At-0 | SA0 | Cell always reads 0 regardless of write | Bitline short to GND, failed pull-up | March C- M2: ⇑(r1) |
| Stuck-At-1 | SA1 | Cell always reads 1 regardless of write | Bitline short to VDD, failed pull-down | March C- M5: ⇑(r0) |
| Transition Fault | TF | Cell can write 0 but not transition to 1 (or vice versa) | Weak write driver, high bitline capacitance | March B, March LR |
| Coupling Fault | CF | A write to cell A forces cell B to a value | Capacitive coupling between adjacent bitlines | March LR, March SS |
| Address Decoder Fault | AF | Two addresses map to same cell, or an address maps nowhere | Decoder logic defect, wordline short | March C-, March Y |
A March element is written as ⇑/⇓(ops) — an arrow indicates address traversal direction, and ops are the ordered read/write operations per cell. March C- has 10n complexity (10 operations per cell) and detects SAF, TF, CF, and AF.
// March C- SystemVerilog behavioral model (simplified) task march_c_minus(input int size); // M0: ascending write 0 for (int i = 0; i < size; i++) mem_write(i, 0); // M1: ascending read 0, write 1 for (int i = 0; i < size; i++) begin check(mem_read(i), 0, i, "M1 r0"); mem_write(i, 1); end // M2: ascending read 1, write 0 for (int i = 0; i < size; i++) begin check(mem_read(i), 1, i, "M2 r1"); mem_write(i, 0); end // M3: descending read 0, write 1 for (int i = size-1; i >= 0; i--) begin check(mem_read(i), 0, i, "M3 r0"); mem_write(i, 1); end // M4: descending read 1, write 0 for (int i = size-1; i >= 0; i--) begin check(mem_read(i), 1, i, "M4 r1"); mem_write(i, 0); end // M5: ascending read 0 for (int i = 0; i < size; i++) check(mem_read(i), 0, i, "M5 r0"); endtask
Click any memory cell to inject a fault, then press Run Test to watch the March C- algorithm sweep through the 4×4 array. The analyzer will catch every fault you inject.
Each memory's BIST controller is accessed via a standardized IEEE 1500 test wrapper. BIST_EN, SCAN_EN, and CLK are routed through a TAP controller, enabling JTAG-based production test.
MBIST runs the memory at functional clock frequency, catching timing-dependent faults (slow writes, sense amp margin) that scan-based tests running at lower speed would miss.
Advanced MBIST includes Built-In Redundancy Analysis (BIRA). When a failing cell is found, BIRA selects a spare row/column and programs an eFuse to remap around the defect at power-on.
MBIST can run at power-on (BIST before boot) to detect infant mortality and wear-out faults in the field, not just at production test — critical for automotive ISO 26262 and aerospace applications.
| Aspect | MBIST | ATPG (Scan) |
|---|---|---|
| Target | Memory bitcells, bitlines, wordlines | Logic gates, flip-flops |
| Pattern source | On-chip March FSM | External ATE from .stil file |
| Speed | At functional clock speed | Typically slower (shift mode) |
| Coverage metric | Fault model coverage (SAF, TF, CF) | Stuck-at, transition, path delay |
| Test time | O(n) — linear in cells | O(n²) for ATPG on large cones |
| Required for memories? | Yes — mandatory | No (can't reach bitcells) |
MBIST (Memory Built-In Self-Test) is an on-chip DFT technique that places a compact test controller adjacent to each memory array. It runs March algorithms — sequences of write/read operations — to detect stuck-at, transition, coupling, and address decoder faults without any external ATE pattern generation.
March C- is a 10n-complexity algorithm (n = number of cells): ⇑(w0); ⇑(r0,w1); ⇑(r1,w0); ⇓(r0,w1); ⇓(r1,w0); ⇑(r0). It detects stuck-at faults, transition faults, idempotent coupling faults, and address decoder faults. The "-" means the final read element order is flexible (not strictly ascending).
Scan chains test sequential logic by shifting known data through flip-flops. Memory arrays are 2D structures requiring address-based access. For an n-bit memory, scan insertion would require n shift operations per access — completely impractical for the 70–80% of SoC area occupied by memory. MBIST is the standard solution.
SA0: the cell always reads 0 regardless of what was written — caused by a bitline shorted to GND or a failed pull-up transistor. SA1: always reads 1 — caused by VDD short or failed pull-down. March C- catches both: M2 detects SA0 (expects to read back 1 after writing 1), M5 detects SA1 (expects to read 0 at the end).
ATPG generates test patterns for combinational/sequential logic via scan chains. MBIST is specific to memory arrays — it tests bitcells, bitlines, wordlines, sense amplifiers, and address decoders using March algorithms. A complete SoC test strategy requires both: ATPG for logic, MBIST for all embedded SRAMs, ROMs, and register files.