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UVM Architecture
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By EcrioniX · Updated Jun 6, 2026

Every component, every connection, every transaction — animated live. Click any box to explore its role, code, and wiring.

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UVM Phase Progression
build_phase
connect_phase
run_phase
check_phase
report_phase
ENVIRONMENT — uvm_env AGENT — uvm_agent (ACTIVE) TEST uvm_test · run_test() click to explore SEQUENCER uvm_sequencer seq_item_export DRIVER uvm_driver get_next_item / item_done MONITOR uvm_monitor analysis_port.write() SCOREBOARD uvm_scoreboard uvm_analysis_imp · write() COVERAGE COLLECTOR uvm_subscriber covergroup · coverpoint CONFIG DATABASE uvm_config_db set() / get() · virtual if VIRTUAL INTERFACE virtual my_if · clocking block DUT Device Under Test RTL Module — not in UVM hierarchy seq_item_port ap.write() ap.write() vif.get() observe pin drive
👆 Click any component in the diagram to explore its role, responsibilities, and code
Component Legend — click to explore
Test
uvm_test
Sequencer
uvm_sequencer
Driver
uvm_driver
Monitor
uvm_monitor
Scoreboard
uvm_scoreboard
Coverage
uvm_subscriber
Config DB
uvm_config_db
Virtual IF
virtual interface
DUT
RTL module
Frequently Asked Questions
What are the main components of a UVM testbench?
A UVM testbench has: uvm_test (top-level controller), uvm_env (container for agents and checkers), uvm_agent (contains sequencer + driver + monitor), uvm_sequencer (routes transactions to the driver), uvm_driver (drives DUT signals), uvm_monitor (passively observes the DUT), uvm_scoreboard (checks correctness), and coverage collectors. All communicate through TLM ports and analysis ports.
How does a transaction move through UVM?
A sequence generates items and starts them on the sequencer via seq.start(sequencer). The sequencer routes each item to the driver's seq_item_port.get_next_item(). The driver drives DUT signals through a virtual interface, then calls item_done(). The monitor independently observes DUT signals and reconstructs transactions, then broadcasts them via analysis_port.write() to the scoreboard and coverage collector simultaneously.
What is the UVM phase sequence?
build_phase → create child components (bottom-up). connect_phase → wire TLM ports. run_phase → main simulation (time-consuming, parallel across all components). check_phase → report errors. report_phase → print final coverage and stats. The run_phase uses time-consuming tasks; all other phases use functions.
What is uvm_config_db used for?
uvm_config_db is a global hierarchical database for passing configuration between UVM components. The testbench top module calls set() to store a virtual interface (or integer, string, object), and each driver or monitor calls get() in build_phase to retrieve it. The path argument ("uvm_test_top.*") determines which components can see the value.

UVM Architecture — How a Modern Testbench Is Built

The Universal Verification Methodology (UVM) is the industry-standard framework for building reusable, scalable testbenches in SystemVerilog. Rather than every team inventing its own structure, UVM provides a proven architecture of standard components and a base-class library, so verification environments look familiar and components can be shared between projects.

A UVM testbench is organised as a hierarchy of objects, each with a clear responsibility. Transactions (sequence items) flow from sequences, through a driver onto the interface, while a monitor observes activity and feeds checkers and coverage. This separation of stimulus generation, driving, monitoring and checking is what makes UVM environments maintainable as a design grows.

The core components

UVM also brings the factory, configuration database and phasing that let you override components and pass settings cleanly through the hierarchy. Mastering this architecture is essential for any verification role, and it builds directly on the SystemVerilog OOP and constrained-random features covered elsewhere in this section.