What is the difference between always @(*) and always @(posedge clk)?

always @(*) is a combinational block — it re-evaluates whenever any input changes, like pure logic gates. It should have no memory (every output must be assigned in every execution path). always @(posedge clk) is a sequential block — it only evaluates on rising clock edges, modeling flip-flops that store state.

What is a sensitivity list in Verilog?

The sensitivity list is the list of signals after always @ that trigger re-evaluation of the block. always @(a, b, c) means: re-run the block whenever a, b, or c changes. The wildcard @(*) automatically includes all signals read inside the block, which is the recommended approach for combinational logic.

What causes latch inference in Verilog?

A latch is inferred when a reg inside a combinational always @(*) block is not assigned in every possible execution path. For example, if (en) out = data; — when en is 0, out retains its old value (like a latch). To avoid this: use else clauses, always assign a default at the top of the block, or use case with a default.

Can you mix always and assign in the same module?

Yes. A module can have multiple assign statements and multiple always blocks, all running concurrently. Each always block and assign drives different signals. You cannot drive the same wire from both assign and always — that creates a multi-driver conflict.

What is a continuous assignment in Verilog?

A continuous assignment (assign keyword) continuously drives a wire based on the right-hand side expression. Whenever any signal on the RHS changes, the LHS is immediately updated. It models combinational logic directly without needing an always block. Only net types (wire) can be driven by assign.

Why must reset be included in the always block sensitivity list?

For asynchronous reset (the most common style), the reset signal must be in the sensitivity list so the flip-flop responds immediately when reset is asserted, without waiting for a clock edge. Example: always @(posedge clk or negedge rst_n). For synchronous reset, rst_n is NOT in the sensitivity list — reset only takes effect at the next clock edge.

What is the difference between blocking and non-blocking assignments in Verilog?

= (blocking) executes sequentially within a block — the next statement sees the updated value. <= (non-blocking) schedules an update — all updates happen simultaneously at the end of the time step. Use = in combinational always @(*) blocks. Use <= in sequential always @(posedge clk) blocks. Mixing them leads to race conditions.

Tutorial 05 · Verilog Series

Verilog always & assign Blocks

The assign statement and always block are the two fundamental ways to describe hardware behavior in Verilog. Getting them right — especially the sensitivity list and the combinational/sequential split — is the most important skill in RTL design.

assign (continuous) always @(*) always @(posedge clk) Sensitivity List Latch Inference Async/Sync Reset

Three ways to describe hardware: continuous assign, combinational always @(*), and sequential always @(posedge clk) — all run in parallel.

1. Continuous assign Statement

The assign statement drives a wire continuously. Whenever the right-hand side expression changes, the left-hand side updates immediately.

verilog

module logic_gates (
    input  a, b, sel,
    output y_and, y_or, y_mux
);
    assign y_and = a & b;
    assign y_or  = a | b;
    assign y_mux = sel ? a : b;   // mux
endmodule

Only drives wire types (or output ports not declared reg)
Multiple assign statements all evaluate concurrently
No begin / end needed — each assign is one statement
Cannot have procedural statements (if, for, etc.) — use always for those

Multi-driver rule: A wire can only be driven by one assign (or one module output). Driving from two assign statements creates a multi-driver conflict — the result is X in simulation.

2. The always Block

An always block runs repeatedly (forever) in simulation. It is triggered by events in its sensitivity list. The hardware it infers depends on what triggers it.

verilog — structure

always @(/* sensitivity list */) begin
    // procedural statements
    // if / case / for / while
    // = (blocking) or <= (non-blocking) assignments
end

Key properties:

Drives reg types only (not wire)
Multiple always blocks in the same module all run concurrently
Each signal may only be driven by one always block
A module can have any number of always blocks

3. Sensitivity List

The sensitivity list is the event list that triggers the always block. Three forms:

verilog

// 1. Explicit list — trigger on any change to a or b or c
always @(a, b, sel) begin
    out = sel ? a : b;
end

// 2. Wildcard @(*) — automatically includes all signals read inside
always @(*) begin
    out = sel ? a : b;
end

// 3. Edge-triggered — trigger only on posedge or negedge
always @(posedge clk) begin
    q <= d;
end

// 4. Multiple edges (async reset)
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= 0;
    else        q <= d;
end

Best practice: Always use @(*) for combinational blocks — never list signals manually. Forgetting a signal in an explicit list creates a simulation/synthesis mismatch and is a very common bug.

4. Combinational always @(*)

A combinational always block models logic without memory. Rules:

Use @(*) — wildcard picks up all inputs automatically
Use blocking assignment (=)
Assign a value to every output in every code path (no latch!)
May use if / else, case, for loops

verilog — 4:1 mux using always @(*)

module mux4 (
    input  [1:0] sel,
    input        d0, d1, d2, d3,
    output reg   out
);
    always @(*) begin
        case (sel)
            2'b00: out = d0;
            2'b01: out = d1;
            2'b10: out = d2;
            default: out = d3;  // covers 2'b11 and any X
        endcase
    end
endmodule

5. Sequential always @(posedge clk)

A sequential always block models flip-flops — state that changes only on clock edges. Rules:

Sensitivity list: @(posedge clk) or @(posedge clk or negedge rst_n)
Use non-blocking assignment (<=)
It is OK not to assign a signal — the flip-flop retains its old value

verilog — D flip-flop

module dff (
    input      clk, d,
    output reg q
);
    always @(posedge clk)
        q <= d;      // non-blocking: q captures d on rising edge
endmodule

verilog — 8-bit shift register with enable

module shift_reg8 (
    input       clk, rst_n, en, sin,
    output reg [7:0] q
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)    q <= 8'b0;
        else if (en) q <= {q[6:0], sin};  // shift left, insert sin
        // en=0: q retains its value (flip-flop holds state)
    end
endmodule

6. Asynchronous vs Synchronous Reset

Asynchronous Reset (most common)

Reset takes effect immediately, regardless of clock. Include rst_n in sensitivity list.

Synchronous Reset

Reset only takes effect on the next clock edge. rst_n is NOT in the sensitivity list.

verilog

// Asynchronous active-low reset
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) q <= 0;
    else        q <= d;
end

// Synchronous active-high reset
always @(posedge clk) begin
    if (rst) q <= 0;    // rst NOT in sensitivity list
    else     q <= d;
end

Industry convention: Active-low asynchronous reset (rst_n) is the most widely used style in professional RTL. Most standard cell libraries have both D and RB (reset-bar) pins on their flip-flops. Always name your reset signal with _n suffix to indicate active-low.

7. Latch Inference — How to Avoid It

A latch is inferred when a reg inside always @(*) is not assigned in every execution path. The synthesizer must insert a level-sensitive latch to hold the old value.

verilog — BAD: latch inferred

always @(*) begin
    if (en) out = data;   // when en=0: out retains old value → LATCH
end

verilog — GOOD: no latch (three methods)

// Method 1: always use else
always @(*) begin
    if (en) out = data;
    else    out = 8'b0;  // explicit else: out always assigned
end

// Method 2: assign default at top of block
always @(*) begin
    out = 8'b0;           // default: covers all unspecified paths
    if (en) out = data;   // override only when en=1
end

// Method 3: case with default
always @(*) begin
    case (sel)
        2'd0: out = a;
        2'd1: out = b;
        default: out = 8'b0;  // covers 2'd2, 2'd3, X
    endcase
end

Why latches are bad in RTL: Latches are level-sensitive — they are transparent whenever the enable is high. This creates timing paths that are very difficult to close with static timing analysis (STA). Most teams ban latches from RTL unless deliberately intended (e.g. power-domain isolation cells). Synthesis tools will warn you: "latch inferred for signal X".

8. Summary Table

Feature	assign	always @(*)	always @(posedge clk)
Drives	wire	reg	reg
Assignment operator	=	= (blocking)	<= (non-blocking)
Triggered by	Any RHS change	Any input in @(*)	Rising clock edge
Infers hardware	Combinational	Combinational	Flip-flop
Procedural statements	No	Yes (if/case/for)	Yes (if/case/for)
Missing assignment path	N/A	Latch ⚠️	Flip-flop retains (OK)

9. Full Design Example: 4-bit Up Counter with Load

verilog

module counter4 (
    input        clk, rst_n, load, en,
    input  [3:0] d,
    output [3:0] q,
    output       carry
);
    reg [3:0] count;

    // Sequential block: flip-flops
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)      count <= 4'b0;
        else if (load)  count <= d;
        else if (en)    count <= count + 1;
        // en=0, load=0: count retains value
    end

    // Continuous assigns: combinational outputs
    assign q     = count;
    assign carry = (count == 4'hF) & en;  // carry out on 15→0 rollover
endmodule

Operators in Verilog Blocking vs Non-Blocking