Verilog (Verify Logic) is a Hardware Description Language (HDL) used to model, simulate, and synthesize digital circuits. Created in 1984 by Gateway Design Automation and standardized as IEEE 1364, it describes hardware behavior using constructs like modules, always blocks, and assign statements. Unlike software code that runs sequentially, Verilog describes circuits where many operations happen simultaneously.

What is the difference between Verilog and VHDL?

Verilog and VHDL are both IEEE-standard HDLs. Verilog has C-like syntax, is more concise, and dominates in the US and Asia-Pacific semiconductor industry. VHDL is more verbose and strongly typed, common in European and defense industries. Both can describe the same hardware. For new learners, Verilog (and its superset SystemVerilog) is the better choice for industry relevance.

What are the levels of abstraction in Verilog?

Verilog supports three levels: (1) Behavioral — describes what the circuit does using high-level constructs (like if/else, for loops) without specifying implementation; (2) RTL (Register Transfer Level) — describes how data flows between registers using clocked always blocks and combinational logic, this is what synthesis tools read; (3) Gate-level — describes individual logic gates (and, or, nand) and their connections. RTL is the standard design entry level in industry.

How do I simulate Verilog code?

Write a testbench module (with no ports) that instantiates your design under test (DUT), applies stimulus using initial blocks and #delay, and monitors outputs with $display or $monitor. Compile and simulate with tools like: VCS (Synopsys), Xcelium (Cadence), ModelSim/Questasim (Siemens), or the free Icarus Verilog (iverilog) with GTKWave for waveform viewing. The testbench does not get synthesized — it's only for simulation.

Introduction to Verilog HDL – What is Verilog?

Q: What is concurrency in Verilog?

In hardware, all gates operate simultaneously — there is no sequential order. Verilog models this with concurrency: all always blocks, assign statements, and module instances run in parallel at any given simulation time. This is the fundamental difference from software programming. When you write two always blocks, they execute at the same time, not one after the other.

Q: What is the difference between Verilog and SystemVerilog?

SystemVerilog (IEEE 1800) is a superset of Verilog that adds verification features (classes, interfaces, assertions, randomization) and design enhancements (logic type, always_comb, always_ff, packed structs, enums). Industry RTL is now written almost exclusively in SystemVerilog. Verilog knowledge transfers directly — SystemVerilog just adds more features on top.

Q: Is Verilog a programming language?

Verilog is a hardware description language, not a programming language. The key difference: software code executes sequentially on a processor, while Verilog describes physical hardware that operates in parallel. When you write Verilog, you are designing circuits — flip-flops, gates, and wires — not writing instructions for a CPU. Simulation tools execute Verilog to verify behavior, and synthesis tools translate it into actual gate-level netlists.

Core Concept

Hardware is Concurrent — That's the Big Difference

In software, instructions run one at a time, line by line. In hardware, everything runs at the same time. This is the most important concept to internalize before writing a single line of Verilog.

      Key rule: In Verilog, assign a = b + c; and assign d = e & f; both evaluate simultaneously. The order you write them on the page does not matter. Hardware has no concept of "running line 1 before line 2."
    

Background

What is Verilog HDL?

Verilog (short for Verify Logic) is a Hardware Description Language (HDL) created in 1984 by Phil Moorby at Gateway Design Automation. It was standardized as IEEE 1364-1995 and later updated in 2001 (Verilog-2001) with important improvements like ANSI-style port declarations and generate blocks.

Verilog describes digital circuits: the gates, flip-flops, multiplexers, memories, and wiring that form chips. You use it to:

Design — write RTL that a synthesis tool converts to a gate-level netlist
Simulate — verify your design works correctly before fabrication
Model — describe both synthesizable hardware and simulation-only behavior

Today, the industry uses SystemVerilog (IEEE 1800) — a superset of Verilog that adds verification features and better design constructs. Everything you learn in Verilog applies directly to SystemVerilog.

Abstraction Levels

Three Ways to Describe Hardware in Verilog

① Behavioral Level

Describes what the circuit does using high-level constructs. Often not synthesizable. Used in testbenches and architectural modeling.

// Behavioral: describe intent
always @(*) begin
  if (a > b)
    max = a;
  else
    max = b;
end

② RTL Level

Register Transfer Level — describes how data moves between registers. This is what you write for synthesis. Synthesis tools convert RTL to gates.

// RTL: clocked register
always @(posedge clk)
  if (rst_n == 1'b0)
    q <= 8'h00;
  else
    q <= d;

③ Gate Level

Uses primitive gate instances directly. This is what synthesis tools output, not what engineers write by hand (except for special cases).

// Gate-level: explicit gates
and  g1(out1, a, b);
or   g2(out2, c, d);
nand g3(y, out1, out2);

Choosing an HDL

Verilog vs VHDL vs SystemVerilog

Feature	Verilog (IEEE 1364)	VHDL (IEEE 1076)	SystemVerilog (IEEE 1800)
Syntax style	C-like, concise	Ada-like, verbose	C++ / Verilog superset
Type system	Loose (implicit casting)	Strong, strict	Improved over Verilog
Industry use	US, Asia-Pacific chip design	Europe, defense, aerospace	Modern ASIC/FPGA everywhere
Verification	Limited	Limited	UVM, classes, interfaces, assertions
Synthesis	✓ Full support	✓ Full support	✓ Superset of Verilog
Learn first?	Yes — simple and industry-relevant	If required by course/job	After Verilog basics

Recommendation: Learn Verilog first. Then move to SystemVerilog. VHDL only if your specific company/university requires it.

First Program

Your First Verilog Module — A 2-Input AND Gate

The fundamental unit in Verilog is the module — equivalent to a chip or a sub-circuit. Every Verilog design starts with module and ends with endmodule.

// ============================================================
// Tutorial 01: Your first Verilog module
// A 2-input AND gate
// ============================================================

module and_gate (
  input  wire a,    // first input
  input  wire b,    // second input
  output wire y     // output: y = a AND b
);

  assign y = a & b;  // continuous assignment

endmodule

Breaking it down:

module and_gate — declares a module named and_gate. Name must match the filename (and_gate.v).
input wire a, b — two input ports. wire is the data type — a net driven by logic.
output wire y — one output port.
assign y = a & b — continuous assignment. Whenever a or b changes, y updates immediately.
endmodule — closes the module.

Testbench to Simulate It

// Testbench — no ports, simulation only
module and_gate_tb;

  // Declare test signals
  reg a, b;
  wire y;

  // Instantiate the design under test (DUT)
  and_gate dut (
    .a(a),
    .b(b),
    .y(y)
  );

  // Apply stimulus and check output
  initial begin
    $display("a b | y");
    $display("-------");

    a = 0; b = 0; #10;
    $display("%b %b | %b", a, b, y);  // 0 0 | 0

    a = 0; b = 1; #10;
    $display("%b %b | %b", a, b, y);  // 0 1 | 0

    a = 1; b = 0; #10;
    $display("%b %b | %b", a, b, y);  // 1 0 | 0

    a = 1; b = 1; #10;
    $display("%b %b | %b", a, b, y);  // 1 1 | 1

    $finish;  // end simulation
  end

endmodule

⚡ Mental model tip

The initial block in the testbench runs once at time 0 and executes sequentially — this is the one place where sequential execution is intentional, for applying test stimulus. Your actual design code (assign, always @*) always runs concurrently.

Running Your First Simulation

Free Tools — Simulate Verilog Right Now

You don't need expensive EDA tools to learn Verilog. Use one of these:

EDA Playground

Browser-based simulator at edaplayground.com. Select Icarus Verilog or Synopsys VCS. Paste code and click Run. No install needed.

Icarus Verilog (local)

Free, open-source Verilog simulator. Install on Linux/Mac/Windows.

# compile
iverilog -o sim and_gate.v and_gate_tb.v
# run
vvp sim

ModelSim / Questasim

Free ModelSim PE Student Edition available. Professional tool widely used in universities and small teams.

Quick Summary

5 Rules to Remember from Tutorial 01

Hardware is concurrent. All assign statements and always blocks run in parallel. Order on the page doesn't matter for hardware behavior.
Verilog describes circuits, not programs. You are designing flip-flops, gates, and wires — not writing instructions for a CPU.
Every design is a module. module name ... endmodule is the basic unit. Modules can instantiate other modules.
assign drives wires continuously. assign y = a & b means "wire y is always equal to a AND b" — it reacts instantly to any change in a or b.
Testbenches don't get synthesized. initial blocks, $display, #delay — these are simulation-only constructs.

FAQ

Frequently Asked Questions

What is Verilog HDL?

Verilog is a Hardware Description Language used to model, simulate, and synthesize digital circuits. It describes hardware — gates, flip-flops, and wires — using a C-like syntax. IEEE 1364, created in 1984, standardized by 1995.

Is Verilog a programming language?

No. Verilog is a hardware description language. Software code runs sequentially on a processor; Verilog describes physical circuits that all operate simultaneously. Simulation tools "run" Verilog to verify it, but the output of a real Verilog workflow is a gate netlist, not executable code.

What is the difference between Verilog and SystemVerilog?

SystemVerilog (IEEE 1800) is a superset of Verilog. All valid Verilog is valid SystemVerilog. SV adds verification features (classes, UVM, constrained random, assertions) and design improvements (logic type, always_comb, always_ff, enums, structs). Industry RTL is now almost entirely written in SV.

What is concurrency in Verilog?

All always blocks and assign statements in a Verilog module execute in parallel at any simulation time step. Writing assign a = b+c below assign d = e&f doesn't mean one runs before the other — they are simultaneously active, just like physical gates.

What is RTL?

RTL (Register Transfer Level) is the standard abstraction level for ASIC and FPGA design. RTL code describes how data moves between registers (flip-flops) using clocked always blocks and combinational logic. Synthesis tools read RTL and produce a gate-level netlist. RTL is what you write; gates are what the tool outputs.

How do I simulate Verilog for free?

Use EDA Playground (edaplayground.com) in a browser — free, no install. Or install Icarus Verilog (iverilog) locally — free, open-source, available on all platforms. View waveforms with GTKWave (also free). These tools cover everything in this tutorial series.

Tutorial 01 of 15 Next: Module & Port Declaration →