What is JTAG and what is boundary scan?

JTAG (Joint Test Action Group) defines the IEEE 1149.1 standard for board-level testing via a 4-wire serial interface. Boundary scan adds a chain of boundary scan cells (BSCs) around each I/O pin of an IC. By shifting data through this BSR (boundary scan register) via TDI/TDO, a tester can control and observe every I/O pin without physical probing. This allows testing board interconnects — shorts, opens, stuck-at faults on PCB traces — between chips without bed-of-nails fixtures.

What are the JTAG TAP pins?

IEEE 1149.1 defines 5 dedicated JTAG pins: TDI (Test Data In) — serial data input to scan chain; TDO (Test Data Out) — serial data output from scan chain; TMS (Test Mode Select) — controls TAP controller FSM state transitions; TCK (Test Clock) — JTAG serial clock; TRST (Test Reset, optional) — asynchronous reset of TAP controller. All signals are synchronous to TCK except TRST. TMS is sampled on TCK rising edge; TDO changes on TCK falling edge.

What is the TAP controller FSM?

The TAP (Test Access Port) controller is a 16-state FSM driven by TMS and TCK. Key states: Test-Logic-Reset (TLR) — all DR/IR registers reset to safe state; Run-Test/Idle — idle state between operations; Shift-DR — shift data through selected data register (BSR, BYPASS, etc.); Shift-IR — shift new instruction into the instruction register; Update-DR — parallel load shifted data into output latches; Capture-DR — parallel capture of I/O pin values into BSR. All state transitions are determined by TMS at each TCK rising edge.

What is EXTEST instruction in JTAG?

EXTEST (External Test) is the primary board interconnect test instruction. When loaded into the IR: output BSCs drive chip output pins with test data loaded in the BSR; input BSCs sample the I/O pin values on the next Capture-DR. By driving known values onto output pins and observing what neighboring chips' input BSCs capture, the tester can detect opens (output not reaching neighbor's input), shorts (pin tied to wrong net), and stuck-at faults on PCB traces. EXTEST requires all chips on the board to be JTAG-compliant.

Boundary Scan (JTAG) — IEEE 1149.1 TAP Controller

JTAG Architecture

JTAG Pins & Boundary Scan Register

JTAG architecture: 4–5 dedicated pins (TDI/TDO/TMS/TCK/TRST) drive the TAP controller FSM, which selects which register (IR, BSR, BYPASS) is in the scan path between TDI and TDO.

Pin	Direction	Function
TDI (Test Data In)	Input	Serial data shifted into the selected register (IR or DR) on TCK rising edge
TDO (Test Data Out)	Output	Serial data shifted out of the selected register; changes on TCK falling edge
TMS (Test Mode Select)	Input	Controls TAP controller FSM state transitions; sampled on TCK rising edge
TCK (Test Clock)	Input	JTAG serial clock — all operations synchronous to TCK; independent of system clock
TRST (Test Reset)	Input (optional)	Asynchronous reset of TAP controller to Test-Logic-Reset state; optional in IEEE 1149.1

TAP FSM

TAP Controller — 16-State FSM Key States

TAP FSM key paths: TLR → Run-Test/Idle → Select-DR (for BSR/BYPASS) or Select-IR (to load instruction). Shift-DR/IR shift data; Update-DR/IR applies the shifted data.

Instructions

Standard JTAG Instructions

Instruction	IR Opcode	Selected DR	Purpose
BYPASS	All 1s (e.g. 11111)	1-bit BYPASS register	Short-circuit chip in chain — TDI→TDO in 1 cycle; used when chip is not being tested
SAMPLE/PRELOAD	Device-specific	BSR	Non-intrusive snapshot of I/O pin values during normal operation; preload BSR before EXTEST
EXTEST	All 0s (e.g. 00000)	BSR	Drive BSR values onto output pins and sample input pins — board interconnect test
INTEST	Device-specific	BSR	Apply BSR test data to core logic inputs — internal logic test (optional)
IDCODE	Device-specific	32-bit Device ID register	Read manufacturer ID, part number, version from JTAG device
USERCODE	Device-specific	User-programmable register	Read user-defined ID (FPGA configuration version, etc.)

Interview Q&A

JTAG & Boundary Scan Interview Questions

What is JTAG and what problem does boundary scan solve?

JTAG (IEEE 1149.1) is a 4-wire serial interface standard for testing PCB assemblies. The problem it solves: modern PCBs use BGA packages where I/O pins are hidden under the chip — no physical probe can reach them. Bed-of-nails fixtures are expensive and can't probe all signals. Boundary scan adds a BSC (boundary scan cell) at every I/O pin, forming a serial scan chain accessible via TDI/TDO. A tester can control/observe any I/O pin through the JTAG interface to test board interconnects (opens, shorts, wrong net connections) without physical probing.

What are the 5 JTAG pins and their roles?

TDI (Test Data In): serial data input, sampled on TCK rising edge. TDO (Test Data Out): serial data output, changes on TCK falling edge. TMS (Test Mode Select): drives TAP controller FSM state transitions; sampled on TCK rising edge. TCK (Test Clock): JTAG serial clock, independent of system clock — typically 10–100 MHz. TRST (Test Reset, optional): asynchronous reset of TAP controller to TLR state; if absent, TLR is reached by holding TMS=1 for 5+ TCK cycles. All test operations are synchronous to TCK, allowing low-frequency testing regardless of the chip's functional clock speed.

Describe the TAP controller FSM key states.

The TAP FSM has 16 states driven by TMS at each TCK edge. Key states: (1) Test-Logic-Reset (TLR): all registers reset to idle state; reached by TMS=1 for 5+ cycles; (2) Run-Test/Idle: waiting state between test operations; (3) Select-DR/IR-Scan: entry point to DR or IR path depending on TMS; (4) Capture-DR: parallel load current I/O pin values (or fixed pattern for IR) into shift register; (5) Shift-DR/IR: serial shift — TDI shifts in, TDO shifts out for N TCK cycles; (6) Update-DR/IR: parallel output latch updated with shifted data — new instruction goes active or BSR drives output pins.

What is the EXTEST instruction and how is it used for board testing?

EXTEST is the primary board interconnect test instruction. Sequence: (1) SAMPLE — load current I/O values into BSR (preload safe drive values); (2) Load EXTEST into IR via Shift-IR/Update-IR; (3) Shift-DR to load test values into BSR; (4) Update-DR — BSR output latches drive chip output pins; (5) A neighboring chip's BSCs capture the driven values on its input pins; (6) Shift-DR on the neighbor to unload its captured values via TDO. By systematically driving and observing each net, the tester detects shorts (driven 1 received as 0), opens (driven value not reaching neighbor), and wrong-net connections. All chips on the board must support JTAG for EXTEST to work.

What is the BYPASS register and why is it needed?

BYPASS is a mandatory single-bit register. When BYPASS is selected (IR = all-1s), TDI is routed through the 1-bit register to TDO in 1 clock cycle, bypassing all longer DR (data register) paths. In a board-level JTAG chain with 10 chips, each chip may have a 200-bit BSR. Without BYPASS, shifting data to chip #8 would require clocking through 1600 bits (7 chips × ~200 bits). With BYPASS on chips 1–7 and 9–10, only 7 bits are wasted on those chips, and the full 200-bit shift reaches chip #8 in 207 cycles instead of 1800. Mandatory in all IEEE 1149.1-compliant devices.

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