1. Why Physical Verification Matters
Physical verification is the final quality gate before tape-out. Every silicon wafer costs $10,000–$500,000. A single undetected DRC violation can render an entire multi-million-dollar tape-out worthless — the chip fabricates but doesn't work, or fails yield testing.
Physical verification encompasses two critical checks:
- DRC (Design Rule Check): Verifies layout geometry satisfies foundry manufacturing constraints
- LVS (Layout vs Schematic): Confirms extracted circuit matches the intended netlist
- ERC (Electrical Rule Check): Detects floating nodes, undriven pins, and power issues
- PEX (Parasitic Extraction): Extracts R/C parasitic values for sign-off simulation
Industry Standard
No foundry will accept a tape-out package without clean DRC and LVS sign-off. Tools like Siemens Calibre, Cadence Assura, and Synopsys IC Validator are used by virtually every VLSI design house worldwide.
Physical Verification Flow
Final Layout (GDSII)
│
▼
┌───────────────────────────────────────────────────┐
│ Physical Verification │
│ │
│ ┌─────────┐ ┌─────────┐ ┌─────────┐ ┌──────┐ │
│ │ DRC │ │ LVS │ │ ERC │ │ PEX │ │
│ │Geometry │ │Netlist │ │Elect. │ │Para- │ │
│ │ Rules │ │Match │ │Rules │ │sitics│ │
│ └────┬────┘ └────┬────┘ └────┬────┘ └──┬───┘ │
│ │ │ │ │ │
│ Violations? Mismatches? Errors? R/C values │
│ │ │ │ │ │
│ Fix ◄──────────┤ │ ▼ │
│ │ Fix ◄───────────┘ SPICE sim │
│ ▼ ▼ │
│ Clean DRC Clean LVS ──────────────► Sign-off│
└───────────────────────────────────────────────────┘
│
▼
Tape-Out Package (GDSII → Foundry)
2. Design Rule Checks — Fundamentals
Design rules are foundry-defined geometric constraints derived from the lithography process, etch tolerances, and process variation at a given technology node. Every rule has a physical justification rooted in yield and reliability.
2.1 Spacing Rules
Minimum spacing prevents lithographic bridging — where two features print too close, merging into a short circuit.
Metal Spacing Violation (M7 Layer, 5nm Node)
VIOLATION — Spacing < 20nm:
════════════════════════════════ ← Metal Wire A (20nm wide)
← 15nm gap (VIOLATION) →
════════════════════════════════ ← Metal Wire B (20nm wide)
Result: Short circuit after lithography print
CORRECT — Spacing ≥ 20nm:
════════════════════════════════ ← Metal Wire A (20nm wide)
← 25nm gap (CLEAN) →
════════════════════════════════ ← Metal Wire B (20nm wide)
Result: Reliably fabricated, two distinct wires
Rule parameter in tech file:
LAYER metal7
SPACING 0.020 ; # 20nm minimum
WIDTH 0.020 ; # 20nm minimum width
PITCH 0.040 ; # 40nm minimum pitch (width + spacing)
END metal7
2.2 Width Rules
Minimum line width ensures metal can carry current without resistive losses and doesn't break during CMP (Chemical Mechanical Planarization).
| Technology Node | M1 Min Width | M1 Min Spacing | Via Size |
|---|
| 28nm | 64nm | 64nm | 70×70nm |
| 14nm | 40nm | 40nm | 44×44nm |
| 7nm | 24nm | 24nm | 26×26nm |
| 5nm | 20nm | 20nm | 22×22nm |
| 3nm | 16nm | 16nm | 18×18nm |
2.3 Enclosure Rules
Via enclosure rules ensure metal layers properly overlap vias. If a via isn't fully enclosed by metal on both connected layers, the via resistance spikes and can open under thermal stress.
Via Enclosure — Correct vs Violation
CORRECT Via Enclosure (M6→M7):
M7 Metal ████████████████████████
← enclosure →
┌────┐ ← Via (22×22nm)
│ │
└────┘
← enclosure →
M6 Metal ████████████████████████
Min enclosure on each side: 4nm (per DRC rule)
DRC checks all 4 sides independently
VIOLATION — Insufficient enclosure on right:
M7 Metal ██████████████
┌────┐ ← Via partially hanging off metal!
│ │
└────┘
M6 Metal ██████████████████████
Fix: Extend M7 metal by ≥4nm on right side
2.4 Density Rules
CMP planarization requires uniform metal density. Too sparse → topography hills. Too dense → dishing during polish. Both cause wafer non-planarity and layer-to-layer misalignment.
Density Rule (per tile, typically 50×50µm window):
Metal density = (Total metal area in window) / (Window area)
Minimum density: 20–30% (prevents hills during CMP)
Maximum density: 80–90% (prevents dishing during CMP)
For TSMC N5 Metal 8:
Min density: 25%
Max density: 85%
Window size: 50µm × 50µm
Fix for low density: Add metal fill (dummy metal, floating)
Fix for high density: Remove non-critical metal, or use slotted metal
Slotted Metal Pattern (high-density fix):
██ ██ ██ ██ ██ ██ ██ ██ ← Slotted wide wire
Slots reduce effective density while maintaining current capacity
2.5 Antenna Rules
Antenna violations occur during plasma-based etch steps. Long metal wire segments connected to gate oxide — but not yet to diffusion — accumulate charge. If the ratio of metal area to gate area exceeds the antenna ratio limit, gate oxide ruptures during fabrication.
Antenna Effect — Charge Accumulation
During Metal Etch (before top metal connects to drain/source):
Long Metal Wire (10,000µm²)
═══════════════════════════════════════════
│
┌──────────┴──┐
│ GATE OXIDE │ ← Vulnerable!
│ (thin 2nm) │
└──────────┬──┘
Gate
Plasma charge collected: Q = Metal_area × charge_density
Gate voltage: V = Q / C_oxide = 10,000 × ρ / (ε/t)
If V > V_breakdown (~5V) → Gate oxide ruptured permanently!
Antenna Ratio = Metal_area / Gate_area
Limit (TSMC 5nm M3): 400
Violation: Metal_area / Gate_area > 400
FIXES:
Option 1: Add reverse-biased diode near gate
Diode clamps voltage, bleeds charge safely
Option 2: Break wire with jumper to higher layer
Shorter segments → less charge accumulation
Option 3: Reduce wire length / use different routing path
Antenna Violations Are Reliability Killers
Gate oxide damage from antenna violations isn't always immediately obvious — the chip may pass initial testing but degrade over weeks or months of operation as the weakened oxide breaks down under normal operating voltage. Always fix antenna violations before tape-out.
3. LVS — Layout vs Schematic
LVS answers one fundamental question: "Does the actual silicon topology we laid out match the circuit schematic (netlist) our designers intended?"
3.1 How LVS Works
LVS Comparison Flow
LVS Tool (e.g., Calibre nmLVS):
LAYOUT (GDSII) SCHEMATIC (Netlist)
────────────── ──────────────────
Extract connectivity Read netlist directly
from metal/via layers from synthesis output
│ │
▼ ▼
Layout Netlist Reference Netlist
┌────────────┐ ┌────────────────┐
│ Net: VDD │ │ Net: VDD │
│ connects: │ COMPARE │ connects: │
│ M1, Via1, │ ◄──────────► │ PMOS source, │
│ PMOS src │ │ M1 strap │
└────────────┘ └────────────────┘
│ │
▼ ▼
MATCH? ──────► CLEAN LVS
│
NO MATCH? ──► Report errors:
- Shorts (unintended connection)
- Opens (missing connection)
- Wrong device (wrong transistor W/L)
- Missing devices (cell not in layout)
3.2 Common LVS Errors
| Error Type | Description | Root Cause | Fix Strategy |
|---|
| Short | Two nets merged into one | Metal overlap, missing cut | Add DRC-compliant gap in layout |
| Open | Net split into disconnected parts | Missing via, broken wire | Add via or extend metal |
| Device mismatch | Transistor W/L wrong | Hand edit error | Re-parameterize device in layout |
| Missing net | Pin not connected | Floating output, forgot route | Route the unconnected pin |
| Extra net | Signal in layout not in schematic | Old routing not cleaned up | Delete orphaned metal |
| Floating port | Port defined but not driven | Missing driver cell | Add driver or remove unused port |
3.3 LVS Debugging Example
LVS Short Debug (Two Clock Nets Shorted)
LVS Error Report:
ERROR: SHORT between CLK_A and CLK_B
Net CLK_A: 3,421 nodes
Net CLK_B: 2,889 nodes
Merged as: NET_6312 (6,310 nodes)
Discrepancy: Schematic shows 2 separate nets
Layout shows 1 merged net
Debug Steps:
1. Highlight CLK_A and CLK_B in layout viewer
2. Run DRC on short candidate layers (M3, M4)
3. Find: M3 wire of CLK_A accidentally overlaps CLK_B
Found at: X=2340.15µm, Y=1822.09µm (M3 layer)
Before fix:
CLK_A (M3) ══════════════════════════════
CLK_B (M3) ══════
↑ 2nm overlap → SHORT!
After fix:
CLK_A (M3) ═══════════════════
(cut here) gap CLK_B (M3) ══════
Clean separation ≥ 20nm (DRC compliant)
4. ERC — Electrical Rule Checks
ERC catches circuit-level issues that DRC/LVS miss: floating inputs, missing power connections, and latch-up vulnerabilities.
Common ERC Rules:
1. No floating input gates:
Every gate input must be driven (logic 0, 1, or valid signal)
Floating → random logic state → unpredictable behavior
2. No multiple drivers on same net:
X-state (bus contention) can damage output drivers
Fix: Add tri-state enables or bus muxes
3. Latch-up check (CMOS specific):
P-well and N-well taps must be placed every 30–50µm
Latch-up = PNPN thyristor triggers → catastrophic short
Fix: Increase tap density, add guard rings
4. ESD (Electrostatic Discharge) rules:
Every I/O pin must have ESD protection clamp
Missing ESD → zapped transistors during board assembly
Clamp area: 50–200µm² per pin (typical)
5. PEX — Parasitic Extraction
PEX extracts resistance (R) and capacitance (C) from routed metal. These parasitics change signal delays and must be included in final timing sign-off.
Parasitic RC Model of a Metal Wire
R1 R2 R3
A ──┤████├──┤████├──┤████├── B
1Ω 1Ω 1Ω
│ │ │
═╪═ ═╪═ ═╪═
2fF 2fF 2fF
GND GND GND
Wire: L=100µm, W=0.5µm (M5, 7nm node)
Total R = 3Ω (0.03Ω/µm × 100µm)
Total C = 6fF (0.06fF/µm × 100µm)
Signal delay added: τ = 0.69 × R × C = 0.69 × 3 × 6e-15 = 12.4ps
After PEX extraction:
Pre-PEX timing: 85ps (cell delays only)
Post-PEX timing: 97.4ps (cells + wire RC)
Wire RC added 14.6% extra delay!
→ May cause timing violation on tight path
→ Fix: Upsize driver, add buffer, or use wider metal
6. Verification Tools Comparison
| Tool | Vendor | Strength | Typical Runtime (100M cells) |
|---|
| Calibre DRC/LVS | Siemens EDA | Industry gold standard, most foundry-certified | 4–12 hours |
| Assura DRC/LVS | Cadence | Tight integration with Cadence Virtuoso flow | 5–15 hours |
| IC Validator | Synopsys | Fastest runtime, good StarRC integration | 2–8 hours |
| PVS | Cadence | Massively parallel, good for huge designs | 1–6 hours |
| Quantus PEX | Cadence | Best-in-class parasitic accuracy | 6–18 hours |
| StarRC | Synopsys | Fast extraction, tight timing closure loop | 3–10 hours |
7. Real-World DRC/LVS at Apple & Samsung
Apple A17 Pro (3nm, TSMC N3B)
- Design area: ~88mm², 19 billion transistors
- DRC rules: ~3,000 individual rules in TSMC N3B ruleset
- Initial DRC violations (after routing): ~250,000
- Sign-off DRC violations: 0 (mandatory for tape-out)
- DRC closure iterations: 12 (spread over 4 weeks)
- LVS run time: ~8 hours (distributed compute cluster)
- LVS mismatches at sign-off: 0
Samsung Exynos 2400 (4nm, Samsung SF4)
- Design area: ~135mm², 10 billion transistors
- DRC rules: ~2,500 rules (Samsung SF4 PDK)
- Unique challenge: Samsung rules include MBCFET-specific layout constraints (multi-bridge-channel FET)
- Antenna violations at first run: ~15,000 (high due to 10-layer metal stack)
- Resolved via diode insertion and wire jumpers
8. DRC/LVS Sign-Off Workflow
Iterative DRC Closure (Real Chip Flow)
Week 1 — First DRC run after detailed routing:
Total violations: 284,000
Breakdown:
Spacing violations: 120,000 (43%) → ECO route fixes
Density violations: 80,000 (28%) → Metal fill insertion
Enclosure issues: 50,000 (18%) → Via adjustment
Antenna: 34,000 (12%) → Diode insertion
Week 2 — After ECO fixes:
Total violations: 42,000
Spacing: 8,000 Density: 18,000 Enclosure: 12,000 Antenna: 4,000
Week 3 — After fill completion and re-route:
Total violations: 1,200
(Mostly in tight bus areas and macro edges)
Week 4 — Targeted fixes by physical designers:
Total violations: 0 ✓ CLEAN SIGN-OFF
Lesson: DRC closure is iterative.
Every fix can introduce new violations — careful!
Tools run "incremental DRC" to check only changed areas.
9. Checklist: DRC & LVS Sign-Off
Production Sign-Off Checklist
- ✅ DRC clean (zero violations): All foundry design rules satisfied
- ✅ LVS clean (zero mismatches): Layout matches post-synthesis netlist
- ✅ ERC clean: No floating inputs, no bus contention
- ✅ Antenna violations resolved: Diodes inserted or wires split
- ✅ Metal fill inserted: All layers meet density min/max
- ✅ Via redundancy added: Critical nets use double vias
- ✅ PEX extracted: RC parasitics captured for timing sign-off
- ✅ Post-PEX timing met: All paths pass setup/hold with parasitics
- ✅ ESD protection verified: All I/O pins have qualified clamps
- ✅ Latch-up guard rings: P-well and N-well taps within rules
- ✅ Foundry PDK version locked: Correct tech file used for sign-off
- ✅ GDSII export verified: No flattening errors, correct layers
Next — Day 7: Deep-dive into timing closure — static timing analysis, path-based analysis, and multi-corner multi-mode verification.