1. What is Signal Integrity?
Signal integrity (SI) is the study of how electrical signals degrade as they travel through interconnects. In early CMOS (1µm nodes), interconnect delays were negligible. By the time we reached 180nm, wires contributed ~30% of path delay. At 5nm, interconnect often contributes 60–80% of total delay — and crosstalk noise is a dominant failure mode.
Key signal integrity problems in modern VLSI:
- Crosstalk delay: Adjacent wire switching changes victim wire timing
- Crosstalk noise (glitch): Induced voltage on victim causes false transitions
- IR drop: Resistive drop in power rails causes local voltage sag
- Ground bounce: Simultaneous output switching induces noise on VDD/GND
- Electromigration: High current density degrades metal conductors over time
2. Coupling Capacitance — The Crosstalk Mechanism
Metal wires running parallel accumulate mutual capacitance. The electric field between two wires creates a capacitive coupling path. When the aggressor wire transitions, current flows through this capacitor to the victim wire.
Coupling Capacitance Between Adjacent Wires
Cross-section view (M5 layer, 7nm node):
AGGRESSOR wire VICTIM wire
┌──────────────┐ ┌──────────────┐
M6: ════╪══════════════╪═════════════╪══════════════╪════ ← Above
└──────────────┘ └──────────────┘
M5: ════╔══════════════╗ ←→ CC ←→ ╔══════════════╗════
║ Aggressor ║ 2fF/µm ║ Victim ║
╚══════════════╝ ╚══════════════╝
│ CGround │ CGround
│ 1fF/µm │ 1fF/µm
─────┴─────────────────────────────┴──── GND
Wire parameters (7nm M5):
Width (W): 0.025µm
Height (H): 0.050µm
Spacing (S): 0.025µm (minimum spacing)
CC (coupling) = ε × H × L / S = ~2fF/µm at min spacing
CG (ground) = ε × W × L / H = ~1fF/µm
Ratio: CC/CG = 2.0 at minimum spacing ← most coupling is lateral!
At 2× minimum spacing: CC/CG ≈ 0.7 (much better)
Coupling Current and Noise Voltage:
I_coupling = CC × dV_aggressor/dt
For aggressor transition 0→1 (800mV swing in 50ps):
dV/dt = 0.8V / 50ps = 16 × 10⁹ V/s = 16 GV/s
CC per µm = 2fF/µm
For 100µm parallel run: CC = 200fF
I_coupling = 200e-15 × 16e9 = 3.2mA peak
Victim noise voltage (victim is resistively driven, Rv = 100Ω):
V_noise = I_coupling × Rv = 3.2mA × 100Ω = 320mV
For 0.8V VDD logic (noise margin ~200mV):
320mV noise > 200mV margin → NOISE VIOLATION!
Victim may glitch to wrong logic state!
3. Crosstalk Delay — Timing Impact
Crosstalk delay occurs when the aggressor and victim switch in opposite directions simultaneously. The coupling capacitor sees the full 2× voltage swing, effectively doubling the capacitive load on the victim driver — slowing it down significantly.
Crosstalk Delay Waveform — In-Phase vs Out-of-Phase
Scenario 1: Aggressor SAME direction as victim (no delay impact):
Aggressor: ─────┐ ┌────────────
└─────┘
Victim: ─────┐ ┌────────────
└─────┘
CC current flows IN → both rising together
Net charge on CC: minimal → NO significant delay change
Scenario 2: Aggressor OPPOSITE direction (WORST CASE delay):
Aggressor: ─────────────┐
└───────── ← falling
Victim: ┌─────────────────── ← rising simultaneously
─────┘
CC sees: Aggressor going -0.8V while victim going +0.8V
Total ΔV across CC = 1.6V (double!)
CC must be charged/discharged by BOTH drivers
Effect on victim rising transition:
Victim driver must overcome: CG (normal load) + 2×CC (Miller effect)
Effective capacitance: Ceff = CG + 2×CC = 1fF + 2×2fF = 5fF
Vs no crosstalk: CG = 1fF only
Delay increase: (5fF/1fF)×base_delay = 5× slower transition!
Typical crosstalk delay in 7nm (100µm parallel run, min spacing):
Without crosstalk: 50ps rise time
With worst-case crosstalk: 180ps rise time (3.6× slower)
Added delay to path: 130ps → timing violation!
Timing sign-off includes crosstalk delay:
SI-aware timing = nominal delay + crosstalk delta delay
Tools: Synopsys CrimeTime (with StarRC SI mode), Cadence Tempus SI
4. Crosstalk Noise — Glitch Analysis
A glitch is a brief spurious transition on a stable (non-switching) victim net. If a victim net should hold logic '1' while its aggressor switches, an injected negative pulse might briefly drag the victim below the logic '1' threshold — causing incorrect sampling.
Crosstalk Glitch — Stable Victim Hit by Aggressor
Aggressor (fast-switching clock or bus):
────────────────────┐ ┌──────────────
└─────────┘
↑ ↑
fall rise
Victim (should be stable at logic 1):
VDD 0.8V ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─ ─
┌──────────┐ ┌──────
0.8V ───────────┘ glitch └───────────┘
↑
Glitch: drops to 0.45V
(below 0.5V threshold)
Flip-flop MAY sample WRONG value!
Parameters:
Glitch peak: 0.35V (below 0.5V logic-0 threshold → marginal)
Glitch duration: 80ps
Analysis:
If victim FF samples during glitch window → functional failure!
Glitch must stay below: VIH_min (0.5V for 0.8V CMOS)
Fix: Increase victim driver strength → lower Rv → smaller V_noise
5. Signal Integrity Fixes
5.1 Spacing Increase
Effect of Spacing on Coupling Capacitance
CC vs Wire Spacing (7nm M5, 100µm parallel run):
Spacing CC per µm Total CC Noise (mV)
─────────────────────────────────────────────
1× min 2.0 fF/µm 200fF 320mV ✗ FAIL
2× min 0.9 fF/µm 90fF 144mV ✓ PASS
3× min 0.5 fF/µm 50fF 80mV ✓ PASS (margin)
4× min 0.3 fF/µm 30fF 48mV ✓ PASS (good)
Trade-off: 4× spacing uses 4× more routing track space
May cause routing congestion elsewhere
Solution: reroute to wider/sparser metal layer instead
5.2 Shield Routing
Insert a grounded wire between aggressor and victim to absorb the coupling current before it reaches the victim.
Shield Wire Between Aggressor and Victim
WITHOUT shield (minimum spacing):
│ Aggressor │ ← CC = 200fF → │ Victim │
Noise: 320mV ✗
WITH shield (grounded metal between):
│ Aggressor │ ← CC_A = 150fF → │ SHIELD │ ← CC_V = 150fF → │ Victim │
GND → absorbs aggressor coupling
Victim CC_V: now driven by GND (AC)
Noise on victim: ~0mV ✓ PASS
Shield routing used on:
- Critical clock signals (timing sensitive)
- Analog reference signals (noise sensitive)
- Reset signals (glitch can cause system crash)
- High-frequency differential pairs
Cost: 1 extra routing track per shield wire
Power: tiny (GND track, no dynamic power)
5.3 Wire Upsizing
Wider victim wires have higher drive current capacity — the same injected noise current produces less voltage sag on a lower-impedance victim driver output.
Victim Driver Strength vs Noise:
V_noise = I_coupling / g_m_victim_driver
g_m = transconductance of victim driver (inversely proportional to output resistance)
Larger drive strength → higher g_m → lower output resistance → less noise
Example:
I_coupling = 3.2mA (same aggressor)
INVX2 driver: Rv = 100Ω → V_noise = 320mV ✗
INVX8 driver: Rv = 25Ω → V_noise = 80mV ✓
Upsize victim driver from X2 to X8: solves noise, adds area/power
Alternative: Move victim to higher metal layer
Higher layers have larger pitch → less coupling per unit length
6. Electromigration (EM)
Electromigration is the gradual displacement of metal atoms by high electron current density. Over years of operation, EM can create voids (opens) or hillocks (shorts) in metal wires — causing latent reliability failures well after shipment.
Black's Equation (EM Lifetime):
MTTF = A × j^(-n) × exp(Ea / kT)
Where:
MTTF = Mean Time To Failure
j = current density (A/µm²)
n = 2 (Black's exponent, empirical)
Ea = activation energy (~0.7 eV for Cu)
k = Boltzmann constant
T = temperature (Kelvin)
EM limits (TSMC N7 Cu metal):
DC current density limit (M5): 2.0 mA/µm (width)
AC/RMS current density limit: 3.5 mA/µm (higher because metal recovers)
Via current limit (single via): 0.2mA per via
Always use double vias on power-critical paths!
10-year reliability requires MTTF ≥ 10 years at T_junction_max
Typical design margin: MTTF ≥ 100 years (10× safety factor)
EM check workflow:
1. Run power analysis to get current per wire segment
2. EM checker (Calibre PERC, Mentor Eldo) flags violations
3. Fix: widen wires, add parallel vias, reduce current sharing
7. Ground Bounce — SSO Effects
Simultaneous Switching Output (SSO) noise occurs when many I/O drivers switch in the same direction at once. The large combined di/dt through the package inductance induces noise on the VDD and GND rails.
SSO Ground Bounce Waveform
Scenario: 64 I/O drivers switching from 1→0 simultaneously:
Individual driver current: 5mA each
Total simultaneous: 64 × 5mA = 320mA step
Package inductance: L_pkg = 2nH (ball-grid array)
V_bounce = L × di/dt = 2nH × 320mA / 0.5ns = 1.28V ← HUGE!
GND voltage waveform (should be 0V):
0V ──────────────────┐
\
-0.3V ─── (peak bounce = 0.3V after decap)
-0.6V
-0.9V
-1.28V (without decap!) ↑ Would destroy I/O timing integrity
With proper on-die decoupling:
I_decap absorbs: 80% of peak current
V_bounce = 1.28V × 20% = 0.256V (still needs margin)
Fixes:
1. Limit SSO: no more than 16 drivers per power island switch together
2. Stagger output switching (add small skew between driver groups)
3. Add more decoupling capacitance near I/O ring
4. Use lower inductance package (flip-chip BGA vs wire-bond)
8. SI Sign-Off Tools
| Tool | Vendor | Function | Key Feature |
|---|
| StarRC | Synopsys | Parasitic extraction (R/CC) | Fastest, widely used for PnR closure |
| Quantus | Cadence | Parasitic extraction | Native Innovus integration |
| PrimeTime SI | Synopsys | Crosstalk timing/noise analysis | Full MCMM SI closure, industry reference |
| Tempus SI | Cadence | SI-aware STA with ECO | Automated SI fixing in routing |
| Calibre PERC | Siemens | EM/IR reliability analysis | Foundry-certified EM checking |
| Voltus | Cadence | Dynamic power/IR analysis | Full-chip dynamic IR with waveform |
9. Signal Integrity Sign-Off Checklist
Production SI Checklist
- ✅ Crosstalk delta delay included in STA: SI-aware timing run with coupling
- ✅ All noise violations fixed: Glitch amplitude < noise margin at all endpoints
- ✅ Critical nets shielded: Clock, reset, and analog reference wires shielded
- ✅ Min spacing enforced on sensitive nets: 2× min spacing for low-noise victims
- ✅ Driver upsizing complete: All noise-violating victims have sufficient drive strength
- ✅ EM checks passed: All wires and vias within current density limits
- ✅ SSO analysis done: I/O switching groups within ground bounce budget
- ✅ Power rail noise verified: Dynamic IR drop analysis with SSO included
- ✅ Parallel run length minimized: Long aggressor-victim parallel segments rerouted
- ✅ Crosstalk report generated: Top-100 worst SI paths reviewed and signed off
Next — Day 10: Hierarchical design and multi-die integration — partition strategies, interface definitions, 2.5D/3D integration, chiplets, and inter-die timing closure.