RTL Problems / Level 4 · Clock Domain Crossing (CDC)
What You Will Learn
By solving Asynchronous FIFO Pointer Synchronization — Multi-Clock Design, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Convert a 4-bit write pointer to Gray code in clk_wr, synchronize it across clock domains into clk_rd using a 2-flop synchronizer, and generate a safe rd_empty flag.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Two-flop synchronizers, Gray code counters, FIFO full/empty detection.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
clk_wr | input | 1 | Write domain clock |
wr_rst_n | input | 1 | Write domain active-low reset |
wr_ptr_bin | input | 4 | Binary write pointer in wr domain |
clk_rd | input | 1 | Read domain clock |
rd_rst_n | input | 1 | Read domain active-low reset |
rd_ptr_gray | input | 4 | Current Gray read pointer in rd domain |
rd_empty | output | 1 | Safe empty flag in read clock domain |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Dual clock domains: `clk_wr` and `clk_rd` are completely asynchronous with independent phases and frequencies.
Synthesis Constraints: Passing RTL simulation does NOT prove absence of metastability in physical silicon.
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Synchronizing binary pointers directly without Gray coding: multi-bit skew causes catastrophic FIFO data corruption.', 'Assuming that passing functional simulation proves CDC safety: RTL simulators do not model analog metastability.']
Silicon & Hardware Engineering Notes
CRITICAL CDC NOTE: Functional simulation only confirms algorithmic logic. True CDC robustness requires static CDC analysis tools to verify clock domains and ensure proper `set_max_delay` constraints between the Gray register and the first synchronizer flop.
Starter RTL Code
module top_module(
input clk_wr,
input wr_rst_n,
input [3:0] wr_ptr_bin,
input clk_rd,
input rd_rst_n,
input [3:0] rd_ptr_gray,
output rd_empty
);
// Synchronize Gray write pointer into read domain and generate rd_empty
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input clk_wr,
input wr_rst_n,
input [3:0] wr_ptr_bin,
input clk_rd,
input rd_rst_n,
input [3:0] rd_ptr_gray,
output rd_empty
);
// Step 1: Register Gray code in write clock domain
reg [3:0] wr_gray_reg;
always @(posedge clk_wr or negedge wr_rst_n) begin
if (!wr_rst_n)
wr_gray_reg <= 4'b0000;
else
wr_gray_reg <= wr_ptr_bin ^ (wr_ptr_bin >> 1);
end
// Step 2: 2-Flop synchronizer into read clock domain
(* ASYNC_REG = "TRUE" *) reg [3:0] sync_q1;
(* ASYNC_REG = "TRUE" *) reg [3:0] sync_q2;
always @(posedge clk_rd or negedge rd_rst_n) begin
if (!rd_rst_n) begin
sync_q1 <= 4'b0000;
sync_q2 <= 4'b0000;
end else begin
sync_q1 <= wr_gray_reg;
sync_q2 <= sync_q1;
end
end
// Step 3: Compare synchronized Gray write pointer with current Gray read pointer
assign rd_empty = (sync_q2 == rd_ptr_gray);
endmodule
Related RTL Problems in Level 4
- Two-Flop Synchronizer — Single-Bit CDC — Design a 2-flip-flop synchronizer to safely pass a single-bit control signal from an asynchronous source into the destination clock domain clk_dst.
- Pulse Synchronizer — Clock-Domain Crossing — Design a Toggle-based Pulse Synchronizer to transfer a single-cycle pulse from a fast clock domain (clk_src) to a slow destination domain (clk_dst).
- Gray Code Counter — Gray Encoding — Implement a 4-bit Gray code counter that advances by exactly one bit per transition: 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100...
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Frequently Asked Questions
What does Asynchronous FIFO Pointer Synchronization — Multi-Clock Design require?
Convert a 4-bit write pointer to Gray code in clk_wr, synchronize it across clock domains into clk_rd using a 2-flop synchronizer, and generate a safe rd_empty flag. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: cdc, industry-rtl, arbiters, clock-domain-crossing, hard, async-fifo. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Asynchronous FIFO Pointer Synchronization — Multi-Clock Design to assess real-world synthesizability and race-condition awareness.