RTL Problems / Level 8 · Industry-Level RTL Challenges
What You Will Learn
By solving AXI-Stream Register Slice, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Break timing critical paths on AXI-Stream interfaces by registering forward payload data and valid flags without degrading throughput.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
| clk | input | 1 | Clock signal |
| rst_n | input | 1 | Active-low reset |
| s_axis_tdata | input | 8 | Slave input stream payload |
| s_axis_tvalid | input | 1 | Slave input valid flag |
| s_axis_tready | output | 1 | Slave backpressure ready |
| m_axis_tdata | output | 8 | Master registered payload |
| m_axis_tvalid | output | 1 | Master registered valid flag |
| m_axis_tready | input | 1 | Downstream ready backpressure |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: Strict synchronous timing aligned to posedge clk or zero-delay combinational propagation.
Synthesis Constraints: Synthesizable Verilog-2001. No # delays in synthesizable RTL.
Starter RTL Code
module top_module #(
parameter DATA_W = 8
)(
input wire clk,
input wire rst_n,
input wire [DATA_W-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
output reg [DATA_W-1:0] m_axis_tdata,
output reg m_axis_tvalid,
input wire m_axis_tready
);
// Your code here
endmodule
Related RTL Problems in Level 8
- Watchdog Timer — A timeout that fires unless it keeps getting "kicked" — the safety-net circuit that resets a hung system when its heartbeat stops arriving.
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- CRC-4 Generator — Compute the 4-bit CRC remainder of an 8-bit message using the CRC-4 (poly x⁴+x+1) bit-serial algorithm, entirely in combinational logic.
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Frequently Asked Questions
What does AXI-Stream Register Slice require?
Break timing critical paths on AXI-Stream interfaces by registering forward payload data and valid flags without degrading throughput. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: protocols, axi, timing, industry. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of AXI-Stream Register Slice to assess real-world synthesizability and race-condition awareness.