Clock Enable Generator — Clock Enable Logic — Verilog Practice Problem & Solution

Generate a single-cycle active-high clock enable pulse (ce) every 4 clock cycles without gating the system clock tree.

RTL Problems / Level 2 · Clocking & Timing

What You Will Learn

By solving Clock Enable Generator — Clock Enable Logic, you will acquire core industry skills:

Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.

Problem Statement & Requirements

Generate a single-cycle active-high clock enable pulse (ce) every 4 clock cycles without gating the system clock tree.

Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.

Objective: Understand synchronous clock rate division, avoiding clock skew from gated clocks, and single-cycle strobe generation.

Prerequisites: Synchronous counters, clock domains, clock enable conventions.

Port List & Interface Timing

The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:

Name	Dir	Width	Description
`clk`	input	1	Master high-frequency clock
`areset_n`	input	1	Active-low asynchronous reset
`ce`	output	1	Single-cycle enable strobe (active 1 out of 4 cycles)

Timing Constraints & Synthesizable RTL Rules

⚡ Synthesizable Implementation Guidelines

Timing Contract: Strobe `ce` must be asserted for exactly one clock period every 4 cycles.

Synthesis Constraints: Do NOT divide the clock net itself. Output `ce` is a synchronous data strobe.

Architectural Deep Dive & Implementation Walkthrough

In high-reliability RTL, never generate divided clocks by toggling a flip-flop (`always @(posedge clk) slow_clk <= ~slow_clk;`). Using `slow_clk` as a clock input elsewhere creates multi-clock domain crossing and clock skew issues. The professional industry pattern is to maintain a single unified master clock tree and distribute single-cycle `ce` pulses.

Common RTL Designer Pitfalls

⚠️ Common Mistakes to Avoid

['Creating ripple clocks instead of synchronous enable strobes.', 'Registering `ce` such that it becomes 2 cycles wide instead of exactly 1 cycle.']

Silicon & Hardware Engineering Notes

🛠️ ASIC vs FPGA Hardware Considerations

Synchronous clock enables keep all registers on the same primary low-skew clock distribution network, simplifying static timing analysis (STA).

Starter RTL Code

module top_module(
  input   clk,
  input   areset_n,
  output  ce
);

  // Generate single-cycle pulse every 4 clock cycles

endmodule

Verified Reference Solution

🔒 Reveal Verified Reference RTL Solution

module top_module(
  input   clk,
  input   areset_n,
  output  ce
);
  reg [1:0] cnt;
  always @(posedge clk or negedge areset_n) begin
    if (!areset_n)
      cnt <= 2'b00;
    else
      cnt <= cnt + 1'b1;
  end
  assign ce = (cnt == 2'b11);
endmodule

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Frequently Asked Questions

What does Clock Enable Generator — Clock Enable Logic require?

Generate a single-cycle active-high clock enable pulse (ce) every 4 clock cycles without gating the system clock tree. Implement it as Verilog module top_module matching the listed ports.

Is this design combinational or sequential?

Tags: sequential, fsm, counters, medium, clock-division. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.

How is my solution graded?

A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.

How does this challenge help with semiconductor interviews?

Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Clock Enable Generator — Clock Enable Logic to assess real-world synthesizability and race-condition awareness.