RTL Problems / Level 2 · Sequential Logic
What You Will Learn
By solving Modulo-10 Counter — Terminal Count, you will acquire core industry skills:
- Synthesizable hardware modeling in standard Verilog-2001 / SystemVerilog.
- Correct handling of interface port contracts, edge-triggered clocks, and active-low/high resets.
- Simulation waveform interpretation and debugging using timing diagrams (VCD traces).
- Architectural avoidance of timing violations, glitching hazards, and synthesis warnings.
Problem Statement & Requirements
Design a Modulo-10 (Decade) counter counting from 0 to 9 with active-low async reset. Roll over from 9 to 0.
Hardware design teams at leading semiconductor firms evaluate these exact port contracts, race-condition assertions, and corner cases during technical design reviews and ASIC engineer interviews.
Prerequisites: Binary counters, equality comparison in sequential blocks.
Port List & Interface Timing
The hidden testbench instantiates top_module. Module port names and bit-widths must match the interface contract exactly:
| Name | Dir | Width | Description |
|---|---|---|---|
clk | input | 1 | Clock signal |
areset_n | input | 1 | Active-low asynchronous reset |
q | output | 4 | Decade count value (0 to 9) |
Timing Constraints & Synthesizable RTL Rules
Timing Contract: When q reaches 9 (4'd9), the next active clock edge resets q to 0.
Synthesis Constraints: Count sequence must be strictly 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0...
Architectural Deep Dive & Implementation Walkthrough
Common RTL Designer Pitfalls
['Checking `if (q == 10)`: this causes the counter to output 10 for one cycle before resetting, making it a modulo-11 counter.', 'Resetting asynchronously on the terminal count, causing severe glitching hazards.']
Silicon & Hardware Engineering Notes
Always perform terminal count reset synchronously (`if (q == 9) q <= 0;`). Asynchronous resets driven by combinational decode logic suffer from transient glitches and race conditions.
Starter RTL Code
module top_module(
input clk,
input areset_n,
output reg [3:0] q
);
// Count from 0 to 9, then wrap back to 0
endmodule
Verified Reference Solution
🔒 Reveal Verified Reference RTL Solution
module top_module(
input clk,
input areset_n,
output reg [3:0] q
);
always @(posedge clk or negedge areset_n) begin
if (!areset_n)
q <= 4'd0;
else if (q == 4'd9)
q <= 4'd0;
else
q <= q + 1'b1;
end
endmodule
Related RTL Problems in Level 2
- D Flip-Flop — Positive-Edge-Triggered Storage — Implement a basic 1-bit positive-edge-triggered D flip-flop without reset.
- D Flip-Flop with Asynchronous Reset — Reset Behavior — Design a D flip-flop with active-low asynchronous reset (areset_n). Reset forces q to 0 immediately, independent of clk.
- D Flip-Flop with Synchronous Reset — Clocked Reset — Implement a D flip-flop with active-high synchronous reset (sync_rst). The reset takes effect only on the rising clock edge.
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Frequently Asked Questions
What does Modulo-10 Counter — Terminal Count require?
Design a Modulo-10 (Decade) counter counting from 0 to 9 with active-low async reset. Roll over from 9 to 0. Implement it as Verilog module top_module matching the listed ports.
Is this design combinational or sequential?
Tags: sequential, fsm, counters, medium, counters. If a clock signal is present in the port table, implement it as sequential logic; otherwise, use continuous assignments or combinational blocks.
How is my solution graded?
A hidden SystemVerilog testbench simulates your module in the cloud judge. You pass when all directed corner cases match the golden model and the VCD timing waveform matches the contract.
How does this challenge help with semiconductor interviews?
Technical interviewers at NVIDIA, Qualcomm, Apple, and Intel routinely ask candidates to code, debug, and explain the timing waveforms of Modulo-10 Counter — Terminal Count to assess real-world synthesizability and race-condition awareness.